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參數(shù)資料
| 型號(hào)： | IDT7290820JG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 9/27頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL SW 2048X2048 84-PLCC |
| 標(biāo)準(zhǔn)包裝： | 30 |
| 系列： | 7200 |
| 類型： | 多路復(fù)用器 |
| 電路： | 1 x 16:16 |
| 獨(dú)立電路： | 1 |
| 電壓電源： | 單電源 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 84-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 84-PLCC（29.21x29.21） |
| 包裝： | 管件 |
| 其它名稱： | 7290820JG |
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17
COMMERCIALTEMPERATURERANGE
IDT7290820 5V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
JTAG SUPPORT
TheIDT7290820JTAGinterfaceconformstotheBoundary-Scanstandard
IEEE-1149.1. This standard specifies a design-for-testability technique called
Boundary-Scan Test (BST). The operation of the boundary-scan circuitry is
controlled by an external test access port (TAP) Controller.
TEST ACCESS PORT (TAP)
The Test Access Port (TAP) provides access to the test functions of the
IDT7290820. It consists of three input pins and one output pin.
Test Clock Input (TCK)
TCK provides the clock for the test logic. The TCK does not interfere with
anyon-chipclockandthusremainindependent.TheTCKpermitsshiftingoftest
data into or out of the Boundary-Scan register cells concurrently with the
operation of the device and without interfering with the on-chip logic.
Test Mode Select Input (TMS)
The logic signals received at the TMS input are interpreted by the TAP
Controller to control the test operations. The TMS signals are sampled at the
rising edge of the TCK pulse. This pin is internally pulled to Vcc when it is not
driven from an external source.
Test Data Input (TDI)
Serial input data applied to this port is fed either into the instruction register
or into a test data register, depending on the sequence previously applied to
the TMS input. Both registers are described in a subsequent section. The
received input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to Vcc when it is not driven from an external source.
Test Data Output (TDO)
Depending on the sequence previously applied to the TMS input, the
contents of either the instruction register or data register are serially shifted out
towards the TDO. The data out of the TDO is clocked on the falling edge of the
TCKpulses.Whennodataisshiftedthroughtheboundaryscancells,theTDO
driver is set to a high impedance state.
Test Reset (
TRST)
Reset the JTAG scan structure. This pin is internally pulled to VCC.
INSTRUCTION REGISTER
InaccordancewiththeIEEE1149.1standard,theIDT7290820usespublic
instructions. The IDT7290820 JTAG Interface contains a two-bit instruction
register.InstructionsareseriallyloadedintotheinstructionregisterfromtheTDI
whentheTAPControllerisinitsshifted-IRstate.Subsequently,theinstructions
are decoded to achieve two basic functions: to select the test data register that
may operate while the instruction is current, and to define the serial test data
register path, which is used to shift data between TDI and TDO during data
register scanning. See Table below for instruction decoding.
Value
Instruction
Function
11
Bypass
Select ByPass Register
10
Sample/Period
Select Boundry Scan Register
01
Sample/Period
Select Boundry Scan Register
00
EXTEST
Select Boundry Scan Register
TEST DATA REGISTER
As specified in IEEE 1149.1, the IDT7290820 JTAG Interface contains two
testdataregisters:
The Boundary-Scan register
The Boundary-Scan register consists of a series of Boundary-Scan cells
arranged to form a scan path around the boundary of the IDT7290820 core
logic.
The Bypass Register
The Bypass register is a single stage shift register that provides a one-bit
path from TDI to its TDO. The IDT7290820 boundary scan register contains
118 bits. Bit 0 in Table 15 Boundary Scan Register is the first bit clocked out.
All three-state enable bits are active high.
JTAG Instruction Register Decoding
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