參數(shù)資料
型號(hào)： IDT7290820JG
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 25/27頁(yè)
文件大?。?/td> 0K
描述： IC DGTL SW 2048X2048 84-PLCC
標(biāo)準(zhǔn)包裝： 30
系列： 7200
類型： 多路復(fù)用器
電路： 1 x 16:16
獨(dú)立電路： 1
電壓電源： 單電源
電源電壓： 4.75 V ~ 5.25 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 84-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 84-PLCC（29.21x29.21）
包裝： 管件
其它名稱： 7290820JG
7
COMMERCIALTEMPERATURERANGE
IDT7290820 5V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
TABLE 1 SWITCHING CON.IGURATION
SWITCHING CON.IGURATIONS
The IDT7290820 can operate at different speeds. To configure the
maximum non-blocking switching data rate, the two DR bits in the IMS register
are used. Following are the possible configurations:
2.048 Mb/s Serial Links (DR0=0, DR1=0)
When the 2.048 Mb/s data rate is selected, the device is configured with
16-input/16-outputdatastreamseachhaving32,64Kbit/schannelseach.This
mode requires a CLK of 4.096 MHz and allows a maximum non-blocking
capacity of 512 x 512 channels.
4.096 Mb/s Serial Links (DR0=1, DR1=0)
When the 4.096 Mb/s data rate is selected, the device is configured with
16-input/16-outputdatastreamseachhaving64,64Kbit/schannelseach.This
mode requires a CLK of 8.192 MHz and allows a maximum non-blocking
capacity of 1,024 x 1,024 channels.
8.192 Mb/s Serial Links (DR0=0, DR1=1)
When the 8.192 Mb/s data rate is selected, the device is configured with
16-input/16-outputdatastreamseachhaving128,64Kbit/schannelseach.This
mode requires a CLK of 16.384 MHz and allows a maximum non-blocking
capacity of 2,048 x 2,048 channels.
Table 1 summarizes the switching configurations and the relationship
between different serial data rates and the master clock frequencies.
INPUT FRAME OFFSET SELECTION
Inputframeoffsetselectionallowsthechannelalignmentofindividualinput
streamstobeoffsetwithrespecttotheoutputstreamchannelalignment(i.e.
F0i).
Although all input data comes in at the same speed, delays can be caused by
variable path serial backplanes and variable path lengths which may be
implemented in large centralized and distributed switching systems. Because
dataisoftendelayed,thisfeatureisusefulincompensatingfortheskewbetween
clocks.
Each input stream can have its own delay offset value by programming the
frameinputoffsetregisters(FOR).Themaximumallowableskewis+4.5master
clock(CLK)periodsforwardwithresolutionof1/2clockperiod.Theoutputframe
offsetcannotbeoffsetoradjusted.SeeFigure5,Table11and12fordelayoffset
programming.
SERIAL INPUT FRAME ALIGNMENT EVALUATION
The IDT7290820 provides the frame evaluation (FE) input to determine
different data input delays with respect to the frame pulse
F0i.
A measurement cycle is started by setting the start frame evaluation (SFE)
bit low for at least one frame. When the SFE bit in the IMS register is changed
from low to high, the evaluation starts. Two frames later, the complete frame
evaluation (CFE) bit of the frame alignment register (FAR) changes from low
to high to signal that a valid offset measurement is ready to be read from bits 0
to 11 of the FAR register. The SFE bit must be set to zero before a new
measurementcyclestarted.
In ST-BUS mode, the falling edge of the frame measurement signal (FE)
isevaluatedagainstthefallingedgeoftheST-BUS framepulse.InGCImode,
therisingedgeofFEisevaluatedagainsttherisingedgeoftheGCIframepulse.
See Table 10 & Figure 4 for the description of the frame alignment register.
This feature is not available when the WFP Frame Alignment mode is
enabled (i.e., when the WFPS pin is connected to VCC).
MEMORY BLOCK PROGRAMMING
The IDT7290820 provides users with the capability of initializing the entire
connectionmemoryblockintwoframes.Tosetbits11to15ofeveryconnection
memorylocation,firstprogramthedesiredpatterninbits5to9oftheIMSregister.
The block programming mode is enabled by setting the memory block
program (MBP) bit of the control register high. When the block programming
enable (BPE) bit of the IMS register is set to high, the block programming data
will be loaded into the bits 11 to 15 of every connection memory location. The
other connection memory bits (bit 0 to bit 10) are loaded with zeros. When the
memory block programming is complete, the device resets the BPE bit to zero.
LOOPBACK CONTROL
Theloopbackcontrol(LPBK)bitofeachconnectionmemorylocationallows
the TX output data to be looped backed internally to the RX input for diagnostic
purposes.
If the LPBK bit is high, the associated TX output channel data is internally
looped back to the RX input channel (i.e., data from TX n channel m routes to
the RX n channel m internally); if the LPBK bit is low, the loopback feature is
disabled. For proper per-channel loopback operation, the contents of frame
delay offset registers must be set to zero.
DELAY THROUGH THE IDT7290820
Theswitchingofinformationfromtheinputserialstreamstotheoutputserial
streams results in a throughput delay. The device can be programmed to
performtime-slotinterchangefunctionswithdifferentthroughputdelaycapabili-
tiesontheper-channelbasis.Forvoiceapplications,variablethroughputdelay
isbestasitensuresminimumdelaybetweeninputandoutputdata.Inwideband
dataapplications,constantthroughputdelayisbestastheframeintegrityofthe
information is maintained through the switch.
The delay through the device varies according to the type of throughput
delay selected in the
V/C bit of the connection memory.
VARIABLE DELAY MODE (
V/C BIT = 0)
In this mode, the delay is dependent only on the combination of source and
destination channels and is independent of input and output streams. The
minimum delay achievable in the IDT7290820 is three time-slots. If the input
channeldataisswitchedtothesameoutputchannel(channeln,framep),itwill
beoutputinthefollowingframe(channeln,framep+1).Thesameistrueifinput
channel n is switched to output channel n+1 or n+2. If the input channel n is
switched to output channel n+3, n+4,..., the new output data will appear in the
same frame. Table 2 shows the possible delays for the IDT7290820 in the
variable delay mode.
Serial Interface
Master Clock Required
Matrix Channel
Data Rate
(MHz)
Capacity
2.048 Mb/s
4.096
512 x 512
4.096 Mb/s
8.192
1,024 x 1,024
8.192 Mb/s
16.384
2,048 x 2,048
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