參數(shù)資料
型號(hào)： IDT723641L15PF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： Quad, High Slew Rate, Single-Supply, Op Amp 14-PDIP -40 to 105
中文描述： 1K X 36 OTHER FIFO, 11 ns, PQFP120
封裝： TQFP-120
文件頁(yè)數(shù)： 4/23頁(yè)
文件大?。?/td> 269K
代理商： IDT723641L15PF
4
IDT723631/723641/723651 CMOS SyncFIFO
512 x 36, 1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Symbol
A0-A35
AE
Name
I/O
I/O 36-bit bidirectional data port for side A.
O
Programmable flag synchronized to CLKB. It is LOW when the number of
words in the FIFO is less than or equal to the value in the almost-empty
register (X).
O
Programmable flag synchronized to CLKA. It is LOW when the number of
empty locations in the FIFO is less than or equal to the value in the almost-full
offset register (Y).
I/O 36-bit bidirectional data port for side B.
I
CLKA is a continuous clock that synchronizes all data transfers through port-A
and may be aynchronous or coincident to CLKB. IR
and
AF
are synchronous
to the LOW-to-HIGH transition of CLKA.
I
CLKB is a continuous clock that synchronizes all data transfers through port-B
and may be asynchronous or coincident to CLKA. OR and
AE
are synchro
nous to the LOW-to-HIGH transition of CLKB.
I
CSA
must be LOW to enable a LOW-to-HIGH transition of CLKA to read or
write data on port-A. The A0-A35 outputs are in the high-impedance state
when
CSA
is HIGH.
I
CSB
must be LOW to enable a LOW-to-HIGH transition of CLKB to read or
write data on port-B. The B0-B35 outputs are in the high-impedance state
when
CSB
is HIGH.
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or
write data on port-A.
I
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or
write data on port-B.
I
FS1/
SEN
and FS0/SD are dual-purpose inputs used for flag offset register
programming. During a device reset, FS1/
SEN
and FS0/SD selects the flag
offset programming method. Three offset register programming methods are
available: automatically load one of two preset values, parallel load from port
A, and serial load. When serial load is selected for flag offset register program-
ming, FS1/
SEN
is used as an enable synchronous to the LOW-to-HIGH
transition of CLKA. When FS1/
SEN
is LOW, a rising edge on CLKA load the
bit present on FS0/SD into the X and Y registers. The number of bit writes
required to program the offset registers is 18/20/22. The first bit write stores
the Y-register MSB and the last bit write stores the X-register LSB.
O
IR is synchronized to the LOW-to-HIGH transition of CLKA. When IR is LOW,
the FIFO is full and writes to its array are disabled. When the FIFO is in
retransmit mode, IR indicates when the memory has been filled to the point of
the retransmit data and prevents further writes. IR is set LOW during reset
and is set HIGH after reset.
I
A HIGH level chooses a mailbox register for a port-A read or write operation.
I
A HIGH level chooses a mailbox register for a port-B read or write operation.
When the B0-B35 outputs are active, a HIGH level on MBB selects data from
the mail1 register for output and a LOW level selects FIFO data for output.
O
MBF1
is set LOW by the LOW-to-HIGH transition of CLKA that writes data to
the mail1 register.
MBF1
is set HIGH by a LOW-to-HIGH transition of CLKB
when a port-B read is selected and MBB is HIGH.
MBF1
is set HIGH by a
reset.
Description
Port-A Data
Almost-Empty Flag
AF
Almost-Full Flag.
B0-B35
CLKA
Port-B Data.
Port-A Clock
CLKB
Port-B Clock
CSA
Port-A Chip Select
CSB
Port-B Chip Select
ENA
Port-A Enable
ENB
Port-B Enable
FS1/
SEN,
FS0/SD
Flag-Offset Select 1/
Serial Enable,
Flag Offset 0/
Serial Data
IR
Input-Ready Flag
MBA
MBB
Port-A Mailbox Select
Port-B Mailbox Select
MBF1
Mail1 Register Flag
3023 tbl 01
相關(guān)PDF資料
PDF描述
IDT723651L30PQF HIGH-SLEW-RATE, SINGLE-SUPPLY OPERATIONAL AMPLIFIERS 14-SOIC -40 to 105
IDT723641L15PQF Quad, High Slew Rate, Single-Supply, Op Amp 14-PDIP -40 to 105
IDT723641L20PF Quad, High Slew Rate, Single-Supply, Op Amp 14-TSSOP -40 to 105
IDT723641L20PQF Quad, High Slew Rate, Single-Supply, Op Amp 14-TSSOP -40 to 105
IDT723641L30PF Quad, High Slew Rate, Single-Supply, Op Amp 14-TSSOP -40 to 105
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT723641L15PF8 功能描述:IC FIFO SYNC 1024X36 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT723641L15PFG 功能描述:IC FIFO SYNC 1024X36 132-PQFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT723641L15PFG8 功能描述:IC FIFO SYNC 1024X36 120-TQFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT723641L15PQF 功能描述:IC FIFO SYNC 1024X36 132-PQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT723641L15PQFG 功能描述:IC FIFO SYNC 1024X36 132-PQFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
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