參數(shù)資料
型號(hào)： IDT723641L15PF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： Quad, High Slew Rate, Single-Supply, Op Amp 14-PDIP -40 to 105
中文描述： 1K X 36 OTHER FIFO, 11 ns, PQFP120
封裝： TQFP-120
文件頁(yè)數(shù)： 12/23頁(yè)
文件大?。?/td> 269K
代理商： IDT723641L15PF
12
IDT723631/723641/723651 CMOS SyncFIFO
512 x 36, 1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
SYNCHRONOUS RETRANSMIT
The synchronous retransmit feature of the IDT723631/
723641/723651 allows FIFO data to be read repeatedly
starting at a user-selected position. The FIFO is first put into
retransmit mode to select a beginning word and prevent on-
going FIFO write operations from destroying retransmit data.
Data vectors with a minimum length of three words can
retransmit repeatedly starting at the selected word. The FIFO
can be taken out of retransmit mode at any time and allow
normal device operation.
The FIFO is put in retransmit mode by a LOW-to-HIGH
transition on CLKB when the retransmit mode (RTM) input is
HIGH and OR is HIGH. The rising CLKB edge marks the data
present in the FIFO output register as the first retransmit data.
The FIFO remains in retransmit mode until a LOW-to-HIGH
transition occurs while RTM is LOW.
When two or more reads have been done past the initial
retransmit word, a retransmit is initiated by a LOW-to-HIGH
transition on CLKB when the read-from-mark (RFM) input is
HIGH. This rising CLKB edge shifts the first retransmit word
to the FIFO output register and subsequent reads can begin
immediately. Retransmit loops can be done endlessly while
the FIFO is in retransmit mode. RFM must be LOW during the
CLKB rising edge that takes the FIFO out of retransmit mode.
When the FIFO is put into retransmit mode, it operates
with two read pointers. The current read pointer operates
normally, incrementing each time a new word is shifted to the
FIFO output register and used by the OR and
AE
flags. The
shadow read pointer stores the SRAM location at the time the
device is put into retransmit mode and does not change until
the device is taken out of retransmit mode. The shadow read
pointer is used by the IR and
AF
flags. Data writes can
proceed while the FIFO is in retransmit mode, but
AF
is set
LOW by the write that stores (512 - Y), (1024 - Y), or (2048 -
Y) words after the first retransmit word for the IDT723631,
IDT723641, or IDT723651, respectively. The IR flag is set
LOW by the 512th, 1024th, or 2048th write after the first
retransmit word for the IDT723631, IDT723641, or IDT723651,
respectively.
When the FIFO is in retransmit mode and RFM is HIGH,
a rising CLKB edge loads the current read pointer with the
shadow read-pointer value and the OR flag reflects the new
level of fill immediately. If the retransmit changes the FIFO
status out of the almost-empty range, up to two CLKB rising
edges after the retransmit cycle are needed to switch
AE
high
(see Figure 11).The rising CLKB edge that takes the FIFO out
of retransmit mode shifts the read pointer used by the IR and
AF
flags from the shadow to the current read pointer. If the
change of read pointer used by IR and
AF
should cause one
or both flags to transmit HIGH, at least two CLKA synchroniz-
ing cycles are needed before the flags reflect the change. A
rising CLKA edge after the FIFO is taken out of retransmit
mode is the first synchronizing cycle of IR if it occurs at time
t
SKEW1
or greater after the rising CLKB edge (see Figure 12).
A rising CLKA edge after the FIFO is taken out of retransmit
mode is the first synchronizing cycle of
AF
if it occurs at time
t
SKEW2
or greater after the rising CLKB edge (see Figure 14).
MAILBOX REGISTERS
Two 36-bit bypass registers are on the IDT723631/723641/
723651 to pass command and control information between
port A and port B. The mailbox-select (MBA, MBB) inputs
choose between a mail register and a FIFO for a port data
transfer operation. A LOW-to-HIGH transition on CLKA writes
A0-A35 data to the mail1 register when a port-A write is
selected by
CSA
, W/
R
A, and ENA with MBA HIGH. A LOW-
to-HIGH transition on CLKB writes B0-B35 data to the mail2
register when a port-B write is selected by
CSB
,
W
/RB, and
ENB with MBB HIGH. Writing data to a mail register sets its
corresponding flag (
MBF1
or
MBF2
) LOW. Attempted writes
to a mail register are ignored while its mail flag is LOW.
When the port-B data (B0-B35) outputs are active, the
data on the bus comes from the FIFO output register when the
port-B mailbox select (MBB) input is LOW and from the mail1
register when MBB is HIGH. Mail2 data is always present on
the port-A data (A0-A35) outputs when they are active. The
mail1 register flag (
MBF1
) is set HIGH by a LOW-to-HIGH
transition on CLKB when a port-B read is selected by
CSB
,
W
/
RB, and ENB with MBB HIGH. The mail2 register flag (MBF2)
is set HIGH by a LOW-to-HIGH transition on CLKA when a
port-A read is selected by
CSA
, W/
R
A, and ENA with MBA
HIGH. The data in a mail register remains intact after it is read
and changes only when new data is written to the register.
相關(guān)PDF資料
PDF描述
IDT723651L30PQF HIGH-SLEW-RATE, SINGLE-SUPPLY OPERATIONAL AMPLIFIERS 14-SOIC -40 to 105
IDT723641L15PQF Quad, High Slew Rate, Single-Supply, Op Amp 14-PDIP -40 to 105
IDT723641L20PF Quad, High Slew Rate, Single-Supply, Op Amp 14-TSSOP -40 to 105
IDT723641L20PQF Quad, High Slew Rate, Single-Supply, Op Amp 14-TSSOP -40 to 105
IDT723641L30PF Quad, High Slew Rate, Single-Supply, Op Amp 14-TSSOP -40 to 105
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT723641L15PF8 功能描述:IC FIFO SYNC 1024X36 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤(pán) 其它名稱:72271LA10PF
IDT723641L15PFG 功能描述:IC FIFO SYNC 1024X36 132-PQFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤(pán) 其它名稱:72271LA10PF
IDT723641L15PFG8 功能描述:IC FIFO SYNC 1024X36 120-TQFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤(pán) 其它名稱:72271LA10PF
IDT723641L15PQF 功能描述:IC FIFO SYNC 1024X36 132-PQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT723641L15PQFG 功能描述:IC FIFO SYNC 1024X36 132-PQFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
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