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參數(shù)資料
| 型號： | IDT723614 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | High-Slew-Rate, Single-Supply Operational Amplifier 8-PDIP 0 to 70 |
| 中文描述： | 與巴士的CMOS SyncBiFIFOO匹配和字節(jié)交換64 × 36 × 2 |
| 文件頁數(shù)： | 8/39頁 |
| 文件大小： | 499K |
| 代理商： | IDT723614 |
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8
COMMERCIAL TEMPERATURE RANGE
IDT723614 CMOS SyncBiFIFO
WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
Synchronized
to CLKB
EFB
L
H
H
H
H
Synchronized
to CLKA
AFA
H
H
H
L
L
Number of 36-Bit
Words in the FIFO1
(1)
0
1 to X
(X+1) to [64-(X+1)]
(64-X) to 63
64
AEB
L
L
H
H
H
FFA
H
H
H
H
L
NOTE:
1. X is the value in the almost-empty flag and almost-full flag offset register.
TABLE 4: FIFO1 FLAG OPERATION
ALMOST EMPTY FLAGS (
AEA
The almost-empty flag of a FIFO is synchronized to the
port clock that reads data from its array. The state machine
that controls an almost-empty flag monitors a write-pointer
and a read-pointer comparator that indicates when the FIFO
SRAM status is almost empty, almost empty+1, or almost
empty+2. The almost-empty state is defined by the value of
the almost-full and almost-empty offset register (X). This
register is loaded with one of four preset values during a
device reset (see Reset above). An almost-empty flag is LOW
when the FIFO contains X or less long words in memory and
is HIGH when the FIFO contains (X+1) or more long words.
Two LOW-to-HIGH transitions of the almost-empty flag
synchronizing clock are required after a FIFO write for the
almost-empty flag to reflect the new level of fill. Therefore, the
almost-empty flag of a FIFO containing (X+1) or more long
words remains LOW if two cycles of the synchronizing clock
have not elapsed since the write that filled the memory to the
(X+1) level. An almost-empty flag is set HIGH by the second
LOW-to-HIGH transition of the synchronizing clock after the
FIFO write that fills memory to the (X+1) level. A LOW-to-
HIGH transition of an almost-empty flag synchronizing clock
begins the first synchronization cycle if it occurs at time t
SKEW2
or greater after the write that fills the FIFO to (X+1) long words.
Otherwise, the subsequent synchronizing clock cycle can be
the first synchronization cycle (see Figure 17 and 18).
,
AEB
)
ALMOST FULL FLAGS (
AFA
The almost-full flag of a FIFO is synchronized to the port
clock that writes data to its array. The state machine that
controls an almost-full flag monitors a write-pointer and read-
pointer comparator that indicates when the FIFO SRAM
status is almost full, almost full-1, or almost full-2. The almost-
full state is defined by the value of the almost-full and almost-
empty offset register (X). This register is loaded with one of
four preset values during a device reset (see Reset above).
An almost-full flag is LOW when the FIFO contains (64-X) or
,
AFB
)
more long words in memory and is HIGH when the FIFO
contains [64-(X+1)] or less long words.
Two LOW-to-HIGH transitions of the almost-full flag
synchronizing clock are required after a FIFO read for the
almost-full flag to reflect the new level of fill. Therefore, the
almost-full flag of a FIFO containing [64-(X+1)] or less words
remains LOW if two cycles of the synchronizing clock have not
elapsed since the read that reduced the number of long words
in memory to [64-(X+1)]. An almost-full flag is set HIGH by the
second LOW-to-HIGH transition of the synchronizing clock
after the FIFO read that reduces the number of long words in
memory to [64-(X+1)]. A LOW-to-HIGH transition of an
almost-full flag synchronizing clock begins the first synchroni-
zation cycle if it occurs at time t
SKEW2
or greater after the read
that reduces the number of long words in memory to [64-
(X+1)]. Otherwise, the subsequent synchronizing clock cycle
can be the first synchronization cycle (see Figure 19 and 20).
MAILBOX REGISTERS
Each FIFO has a 36-bit bypass register to pass command
and control information between port A and port B without
putting it in queue. The mailbox-select (MBA, MBB) inputs
choose between a mail register and a FIFO for a port data
transfer operation. A LOW-to-HIGH transition on CLKA writes
A0-A35 data to the mail1 register when a port A write is
selected by
CSA
, W/
R
A, and ENA with MBA HIGH. A LOW-
to-HIGH transition on CLKB writes B0-B35 data to the mail2
register when a port B write is selected by
CSB
, W/
R
B, and
ENB with both SIZ1 and SIZ0 HIGH. Writing data to a mail
register sets the corresponding flag (
MBF1
or
MBF2
) LOW.
Attempted writes to a mail register are ignored while the mail
flag is LOW.
When the port A data outputs (A0-A35) are active, the
data on the bus comes from the FIFO2 output register when
MBA is LOW and from the mail2 register when MBA is HIGH.
When the port B data outputs (B0-B35) are active, the data on
the bus comes from the FIFO1 output register when either one
Synchronized
to CLKA
EFA
L
H
H
H
H
Synchronized
to CLKB
AFB
H
H
H
L
L
Number of 36-Bit
Words in the FIFO2
(1)
0
1 to X
(X+1) to [64-(X+1)]
(64-X) to 63
64
AEA
L
L
H
H
H
FFB
H
H
H
H
L
TABLE 5: FIFO2 FLAG OPERATION
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT723614L15PF | 功能描述:IC FIFO CLOCKED 64X36X2 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723614L15PF8 | 功能描述:IC FIFO CLOCKED 64X36X2 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723614L15PQF | 功能描述:IC FIFO CLOCKED 64X36X2 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723614L20PF | 功能描述:IC FIFO CLOCKED 64X36X2 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723614L20PF8 | 功能描述:IC FIFO CLOCKED 64X36X2 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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