參數資料
型號: IDT723614
廠商: Integrated Device Technology, Inc.
英文描述: High-Slew-Rate, Single-Supply Operational Amplifier 8-PDIP 0 to 70
中文描述: 與巴士的CMOS SyncBiFIFOO匹配和字節(jié)交換64 × 36 × 2
文件頁數: 31/39頁
文件大?。?/td> 499K
代理商: IDT723614
31
COMMERCIAL TEMPERATURE RANGE
IDT723614 CMOS SyncBiFIFO
WITH BUS MATCHING AND BYTE SWAPPING
64 x 36 x 2
NOTES:
1.
t
SKEW2
is the minimum time between a rising CLKB edge and a rising CLKA edge for
AEA
to transition HIGH in the next CLKA cycle. If the time
between the rising CLKB edge and rising CLKA edge is less than t
SKEW2,
then
AEA
may transition HIGH one CLKA cycle later than shown.
FIFO2 Write (
CSB
= LOW, W/
R
B = HIGH, MBB = LOW), FIFO2 read (
CSA
= LOW, W/
R
A = LOW, MBA = LOW).
Port B size of long word is selected for FIFO2 write by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, t
SKEW2
is referenced from the rising
CLKB edge that writes the last word or byte of the long word, respectively.
2.
3.
Figure 18. Timing for
AEA
when FIFO2 is Almost Empty
NOTES:
1.
t
SKEW2
is the minimum time between a rising CLKA edge and a rising CLKB edge for
AEB
to transition HIGH in the next CLKB cycle. If the time
between the rising CLKA edge and rising CLKB edge is less than t
SKEW2
, then
AEB
may transition HIGH one CLKB cycle later than shown.
FIFO1 Write (
CSA
= LOW, W/
R
A = HIGH, MBA = LOW), FIFO1 read (
CSB
= LOW, W/
R
B = LOW, MBB = LOW).
Port B size of long word is selected for FIFO1 read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte,
AEB
is set LOW by the last word or
byte read of the long word, respectively.
2.
3.
AEB
CLKA
ENB
3146 drw 17
ENA
CLKB
2
1
t
ENS
t
ENH
t
SKEW2
t
PAE
t
PAE
t
ENS
t
ENH
X Long Word in FIFO1
(X+1) Long Words in FIFO1
(1)
Figure 17. Timing for
AEB
when FIFO1 is Almost Empty
AEA
CLKB
ENA
3146 drw 18
ENB
CLKA
2
1
t
ENS
t
ENH
t
SKEW2
t
PAE
t
PAE
t
ENS
t
ENH
(X+1) Long Words in FIFO2
X Long Words in FIFO2
(1)
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