參數(shù)資料
型號(hào)： IDT723612L30PF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： BiCMOS SyncBiFIFOO 64 x 36 x 2
中文描述： 64 X 36 BI-DIRECTIONAL FIFO, 15 ns, PQFP120
封裝： TQFP-120
文件頁數(shù)： 9/29頁
文件大小： 350K
代理商： IDT723612L30PF
9
COMMERCIAL TEMPERATURE RANGE
IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2
SIGNAL DESCRIPTIONS
RESET
The IDT723612 is reset by taking the reset (
RST
) input
LOW for at least four port-A clock (CLKA) and four port-B clock
(CLKB) LOW-to-HIGH transitions. The reset input can switch
asynchronously to the clocks. A device reset initializes the
internal read and write pointers of each FIFO and forces the
full flags (
FFA
,
FFB
) LOW, the empty flags (
EFA
,
EFB
) LOW,
the almost-empty flags (
AEA
,
AEB
) LOW and the almost-full
flags (
AFA
,
AFB
) HIGH. A reset also forces the mailbox flags
(
MBF1
,
MBF2
) HIGH. After a reset,
FFA
is set HIGH after two
LOW-to-HIGH transitions of CLKA and
FFB
is set HIGH after
two LOW-to-HIGH transitions of CLKB. The device must be
reset after power up before data is written to its memory.
A LOW-to-HIGH transition on the
RST
input loads the
almost-full and almost-empty registers (X) with the values
selected by the flag-select (FS0, FS1) inputs. The values that
can be loaded into the registers are shown in Table 1.
FIFO WRITE/READ OPERATION
The state of port-A data A0-A35 outputs is controlled by
the port-A chip select (
CSA
) and the port-A write/read select
(W/
R
A). The A0-A35 outputs are in the high-impedance state
when either
CSA
or W/
R
A is HIGH. The A0-A35 outputs are
active when both
CSA
and W/
R
A are LOW.
Data is loaded into FIFO1 from the A0-A35 inputs on a
LOW-to-HIGH transition of CLKA when
CSA
is LOW, W/
R
A is
HIGH, ENA is HIGH, MBA is LOW, and
FFA
is HIGH. Data is
read from FIFO2 to the A0-A35 outputs by a LOW-to-HIGH
transition of CLKA when
CSA
is LOW, W/
R
A is LOW, ENA is
HIGH, MBA is LOW, and
EFA
is HIGH (see Table 2).
The port-B control signals are identical to those of port A.
The state of the port-B data (B0-B35) outputs is controlled by
the port-B chip select (
CSB
) and the port-B write/read select
(W/
R
B). The B0-B35 outputs are in the high-impedance state
when either
CSB
or W/
R
B is HIGH. The B0-B35 outputs are
active when both
CSB
and W/
R
B are LOW.
Data is loaded into FIFO2 from the B0-B35 inputs on a
LOW-to-HIGH transition of CLKB when
CSB
is LOW, W/
R
B is
HIGH, ENB is HIGH, MBB is LOW, and
FFB
is HIGH. Data is
read from FIFO1 to the B0-B35 outputs by a LOW-to-HIGH
CSB
H
L
L
L
L
L
L
L
W/
R
B
X
H
H
H
L
L
L
L
ENB
X
L
H
H
L
H
L
H
MBB
X
X
L
H
L
L
H
H
CLKB
X
X
↑
↑
X
↑
X
↑
B0-B35 Outputs
In High-Impedance State
In High-Impedance State
In High-Impedance State
In High-Impedance State
Active, FIFO1 Output Register
Active, FIFO1 Output Register
Active, Mail1 Register
Active, Mail1 Register
Port Functions
None
None
FIFO2 Write
Mail2 Write
None
FIFO1 read
None
Mail1 Read (Set
MBF1
HIGH)
Table 3. Port-B Enable Function Table
CSA
H
L
L
L
L
L
L
L
W/
R
A
X
H
H
H
L
L
L
L
ENA
X
L
H
H
L
H
L
H
MBA
X
X
L
H
L
L
H
H
CLKA
X
X
↑
↑
X
↑
X
↑
A0-A35 Outputs
In High-Impedance State
In High-Impedance State
In High-Impedance State
In High-Impedance State
Active, FIFO2 Output Register
Active, FIFO2 Output Register
Active, Mail2 Register
Active, Mail2 Register
Port Functions
None
None
FIFO1 Write
Mail1 Write
None
FIFO2 Read
None
Mail2 Read (Set
MBF2
HIGH)
Table 2. Port-A Enable Function Table
ALMOST-FULL AND
ALMOST-EMPTY FLAG
OFFSET REGISTER (X)
16
12
8
4
FS1
FS0
RST
H
H
L
L
H
L
H
L
↑
↑
↑
↑
Table 1. Flag Programming
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