參數(shù)資料
型號(hào): IDT723612L30PF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: BiCMOS SyncBiFIFOO 64 x 36 x 2
中文描述: 64 X 36 BI-DIRECTIONAL FIFO, 15 ns, PQFP120
封裝: TQFP-120
文件頁數(shù): 7/29頁
文件大?。?/td> 350K
代理商: IDT723612L30PF
7
COMMERCIAL TEMPERATURE RANGE
IDT723612 BiCMOS SyncBiFIFO
64 x 36 x 2
DC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE
AND OPERATING FREE-AIR TEMPERATURE
IDT723612L15 IDT723612L20 IDT723612L30
Min.
Max.
Min.
66.7
15
20
6
8
6
8
4
5
Symbol
f
S
t
CLK
t
CLKH
t
CLKL
t
DS
Parameter
Max.
50
Min.
30
12
12
6
Max.
33.4
Unit
MHz
ns
ns
ns
ns
Clock Frequency, CLKA or CLKB
Clock Cycle Time, CLKA or CLKB
Pulse Duration, CLKA and CLKB HIGH
Pulse Duration, CLKA and CLKB LOW
Setup Time, A0-A35 before CLKA
and B0-B35
before CLKB
Setup Time,
CSA
, W/
R
A before CLKA
;
CSB
,
W/
R
B before CLKB
Setup Time, ENA, before CLKA
; ENB before
CLKB
Setup Time, MBA before CLKA
: MBB before
CLKB
Setup Time, ODD/
EVEN
and PGA before
CLKA
; ODD/
EVEN
and PGB before CLKB
(1)
Setup Time,
RST
LOW before CLKA
or CLKB
(2)
Setup Time, FS0/FS1 before
RST
HIGH
Hold Time, A0-A35 after CLKA
and B0-B35
after CLKB
Hold Time,
CSA
W/
R
A after CLKA
;
CSB
,
W/
R
B after CLKB
Hold Time, ENA, after CLKA
; ENB after CLKB
Hold Time, MBA after CLKA
; MBB after CLKB
Hold Time, ODD/
EVEN
and PGA after CLKA
;
ODD/
EVEN
and PGB after CLKB
(1)
Hold Time,
RST
LOW after CLKA
or CLKB
(2)
Hold Time, FS0 and FS1 after
RST
HIGH
Skew Time, between CLKA
and CLKB
for
EFA
,
EFB
,
FFA
, and
FFB
Skew Time, between CLKA
and CLKB
For
AEA
,
AEB
,
AFA
, and
AFB
t
ENS1
6
6
7
ns
t
ENS2
4
5
6
ns
t
ENS3
4
5
6
ns
t
PGS
4
5
6
ns
t
RSTS
5
6
7
ns
t
FSS
t
DH
5
6
7
ns
ns
2.5
2.5
2.5
t
ENH1
2
2
2
ns
t
ENH2
t
ENH3
t
PGH
2.5
1
1
2.5
1
1
2.5
1
1
ns
ns
ns
t
RSTH
t
FSH
t
SKEW1
(3)
5
4
8
6
4
8
7
4
10
ns
ns
ns
t
SKEW2
(3)
9
16
20
ns
Notes:
1.
2.
3.
Only applies for a clock edge that does a FIFO read.
Requirement to count the clock edge as one of at least four needed to reset a FIFO.
Skew time is not a timimg constraint for proper device operation and is only included to illustrate the timing relation-
ship between CLKA cycle and CLKB cycle.
相關(guān)PDF資料
PDF描述
IDT723612L30PQF BiCMOS SyncBiFIFOO 64 x 36 x 2
IDT723612 Single Low-Power Operational Amplifier 5-SOT-23 -40 to 85
IDT723613L15PQFI CMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 36
IDT723613L20PFI CMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 36
IDT723613L20PQFI CMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 36
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