參數(shù)資料
型號: IDT71V3557S85BG
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: 128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs
中文描述: 128K X 36 ZBT SRAM, 8.5 ns, PBGA119
封裝: 14 X 22 MM, PLASTIC, BGA-119
文件頁數(shù): 15/28頁
文件大?。?/td> 996K
代理商: IDT71V3557S85BG
6.42
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
15
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
DD
= 3.3V +/-5%)
Figure 2. Lumped Capacitive Load, Typical Derating
Figure 1. AC Test Load
AC Test Loads
AC Test Conditions
(V
DDQ
= 3.3V)
Input Pulse Levels
DC Electrical Characterics Over the Operating
Temperature and Supply Voltage Range
(1)
(V
DD
= 3.3V +/-5%)
NOTE:
1. The
LBO,
JTAG and ZZ pins will be internally pulled to V
DD
and ZZ will be internally pulled to V
SS
if it is not actively driven in the application.
NOTES:
1. All values are maximumguaranteed values.
2. At f = f
MAX,
inputs are cycling at the maximumfrequency of read cycles of 1/t
CYC
; f=0 means no input lines are changing.
3. For I/Os V
HD
= V
DDQ
- 0.2V, V
LD
= 0.2V. For other inputs V
HD
= V
DD
- 0.2V, V
LD
= 0.2V.
V
DDQ
/2
50
I/O
Z
0
= 50
5282 drw 04
,
1
2
3
4
20 30 50
100
200
tCD
(Typical, ns)
Capacitance (pF)
80
5
6
5282 drw 05
,
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
|
LI
|
Input Leakage Current
V
DD
= Max., V
IN
= 0V to V
DD
___
5
μA
|
LI
|
LBO,
JTAG and ZZ Input Leakage Current
(1)
V
DD
= Max., V
IN
= 0V to V
DD
___
30
μA
|
LO
|
Output Leakage Current
V
OUT
= 0V to V
CC
___
5
μA
V
OL
Output LowVoltage
I
OL
= +8mA, V
DD
= Min.
___
0.4
V
V
OH
Output High Voltage
I
OH
= -8mA, V
DD
= Min.
2.4
___
V
5282 tbl 21
Symbol
Parameter
Test Conditions
7.5ns
8ns
8.5ns
Unit
Com'l Only
Com'l
Ind
Com'l
Ind
I
DD
Operating Power
Supply Current
Device Selected, Outputs Open,
ADV/
LD
= X, V
DD
= Max.,
V
IN
> V
IH
or < V
IL
, f = f
MAX
(2)
275
250
260
225
235
mA
I
SB1
CMOS Standby Power
Supply Current
Device Deselected, Outputs Open,
V
DD
= Max., V
IN
> V
HD
or < V
LD
,
f = 0
(2,3)
40
40
45
40
45
mA
I
SB2
Clock Running Power
Supply Current
Device Deselected, Outputs Open,
V
DD
= Max., V
IN
> V
HD
or < V
LD
,
f = f
MAX
(2,3)
105
100
110
95
105
mA
I
SB3
Idle Power
Supply Current
Device Selected, Outputs Open,
CEN
> V
IH
, V
DD
= Max.,
V
IN
> V
HD
or < V
LD
, f = f
MAX
(2,3)
40
40
45
40
45
mA
5282 tbl 22
Input Rise/Fall Times
Input Timng Reference Levels
Output Reference Levels
Output Load
0 to 3V
2ns
1.5V
1.5V
Figure 1
5282 tbl 23
相關(guān)PDF資料
PDF描述
IDT71V3557S85BGI 128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs
IDT71V3559S 128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs
IDT71V3559S85BG 128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs
IDT71V3559S85BGI 128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs
IDT71V3559S85BQ 128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter, Flow-Through Outputs
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