參數(shù)資料
型號(hào)： IDT71T75902S75BGI8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： SRAM
英文描述： 1M X 18 ZBT SRAM, 7.5 ns, PBGA119
封裝： 14 X 22 MM, PLASTIC, BGA-119
文件頁(yè)數(shù)： 12/26頁(yè)
文件大?。?/td> 644K
代理商： IDT71T75902S75BGI8
6.42
2
IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Pin Definitions(1)
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
Symbol
Pin Function
I/O
Active
Description
A0-A19
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combination of the rising edge of
CLK, ADV/
LD low, CENlow, and true chip enables.
ADV/
LD
Advance / Load
I
N/A
ADV/
LD is a synchronous input that is used to load the internal registers with new address and control
when it is sampled low at the rising edge of clock with the chip selected. When ADV/
LDis low with the
chip deselected, any burst in progress is terminated. When ADV/
LD is sampled high then the internal
burst counter is advanced for any burst that was in progress. The external addresses are ignored when
ADV/
LD is sampled high.
R/
W
Read / Write
I
N/A
R/
W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or
Write access to the memory array. The data bus activity for the current cycle takes place one clock
cycle later.
CEN
Clock Enable
I
LOW Synchronous Clock Enable Input. When
CEN is sampled high, all other synchronous inputs, including
clock are ignored and outputs remain unchanged. The effect of
CENsampled high on the device
outputs is as if the low to high clock transition did not occur. For normal operation,
CEN must be
sampled low at rising edge of clock.
BW1-BW4
Individual Byte
Write Enables
I
LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write
cycles (When R/
W and ADV/LD are sampled low) the appropriate byte write signal (BW1-BW4) must be
valid. The byte write signal must also be valid on each cycle of a burst write. Byte Write signals are
ignored when R/
W is sampled high. The appropriate byte(s) of data are written into the device one cycle
later.
BW1-BW4 can all be tied low if always doing write to the entire 36-bit word.
CE1, CE2
Chip Enables
I
LOW Synchronous active low chip enable.
CE1 and CE2 are used with CE2 to enable the IDT71T75702/902
(
CE1 or CE2 sampled high or CE2 sampled low) and ADV/LD low at the rising edge of clock, initiates a
deselect cycle. The ZBTTM has a one cycle deselect, i.e., the data bus will tri-state one clock cycle after
deselect is initiated.
CE2
Chip Enable
I
HIGH Synchronous active high chip enable. CE 2 is used with
CE1 and CE2 to enable the chip. CE2 has
inverted polarity but otherwise identical to
CE1 and CE2.
CLK
Clock
I
N/A
This is the clock input to the IDT71T75702/902. Except for
OE, all timing references for the device are
made with respect to the rising edge of CLK.
I/O0-I/O31
I/OP1-I/OP4
Data Input/Output
I/O
N/A
Data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of CLK. The
data output path is flow-through (no output register).
LBO
Linear Burst Order
I
LOW Burst ord er selection input. When
LBO is high the Interleaved burst sequence is selected. When LBO is
low the Linear burst sequence is selected.
LBO is a static input, and it must not change during device
operation.
OE
Output Enable
I
LOW
Asynchronous output enable.
OEmust be low to read data from the IDT71T75702/902. When OE is HIGH
the I/O pins are in a high-impedance state.
OE does not need to be actively controlled for read and
write cycles. In normal operation,
OEcan be tied low.
TMS
Test Mode Select
I
N/A
Gives input command for TAP controller; sampled on rising edge of TCK. This pin has an internal pullup.
TDI
Test Data Input
I
N/A
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an
internal pullup.
TCK
Test Clock
I
N/A
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of
TCK, while test outputs are driven from falling edge of TCK. This pin has an internal pullup.
TDO
Test Data Output
O
N/A
Serial output of registers placed between TDI and TDO. This output is active d epending on the state of
the TAP controller.
TRST
JTAG Reset
(Optional)
ILOW
Optional asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG
reset occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not
used
TRST can be left floating. This pin has an internal pullup. Only available in BGA package.
ZZ
Sleep Mode
I
HIGH
Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
IDT71T75702/902 to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.
This pin has an internal pulldown.
VDD
Power Supply
N/A
2.5V core power supply.
VDDQ
Power Supply
N/A
2.5V I/O Supply.
VSS
Ground
N/A
Ground.
5319 tbl 02
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT71T75902S75PF 功能描述:IC SRAM 18MBIT 75NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 產(chǎn)品變化通告:Product Discontinuation 05/Nov/2008 標(biāo)準(zhǔn)包裝:84 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步 ZBT 存儲(chǔ)容量:4.5M（128K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:119-BGA 供應(yīng)商設(shè)備封裝:119-PBGA（14x22） 包裝:托盤 其它名稱:71V3557SA75BGI
IDT71T75902S75PF8 功能描述:IC SRAM 18MBIT 75NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 產(chǎn)品變化通告:Product Discontinuation 05/Nov/2008 標(biāo)準(zhǔn)包裝:84 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步 ZBT 存儲(chǔ)容量:4.5M（128K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:119-BGA 供應(yīng)商設(shè)備封裝:119-PBGA（14x22） 包裝:托盤 其它名稱:71V3557SA75BGI
IDT71T75902S75PFG 功能描述:IC SRAM 18MBIT 75NS 100TQFP RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，異步 存儲(chǔ)容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF
IDT71T75902S75PFG8 功能描述:IC SRAM 18MBIT 75NS 100TQFP RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，異步 存儲(chǔ)容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF
IDT71T75902S75PFGI 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 18MBIT 7.5NS 100TQFP
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