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參數(shù)資料
| 型號： | IDT71T75902S75BGI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 1M X 18 ZBT SRAM, 7.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, PLASTIC, BGA-119 |
| 文件頁數(shù)： | 1/26頁 |
| 文件大小： | 644K |
| 代理商： | IDT71T75902S75BGI8 |
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APRIL 2004
DSC-5319/08
1
2004 Integrated Device Technology, Inc.
A0-A19
Add ress Inputs
Input
Synchronous
CE1, CE2, CE2
Chip Enable s
Input
Synchronous
OE
Output Enable
Input
Asynchronous
R/
W
Re ad/Write Signal
Input
Synchronous
CEN
Clock Enable
Input
Synchronous
BW1, BW2, BW3, BW4
Individual Byte Write Sele cts
Input
Synchronous
CLK
Clock
Input
N/A
ADV/
LD
Ad vance Burst Address/Load New Ad dress
Input
Synchronous
LBO
Linear/Interleaved Burst Orde r
Input
Static
TMS
Test Mode Select
Input
N/A
TDI
Test Data Input
Input
N/A
TCK
Test Clock
Input
N/A
TDO
Test Data Output
Output
N/A
TRST
JTAG Reset (Optional)
Input
Asynchronous
ZZ
Sleep Mode
Input
Synchronous
I/O0-I/O31, I/OP1-I/OP4
Data Input/Output
I/O
Synchronous
VDD, VDDQ
Co re Po wer, I/O Power
Sup ply
Static
VSS
Ground
Sup ply
Static
5319 tbl 01
Pin Description Summary
The IDT71T75702/902 contain address, data-in and control signal
registers. The outputs are flow-through (no output data register). Output
enable is the only asynchronous signal and can be used to disable the
outputs at any given time.
A Clock Enable (
CEN)pinallowsoperationoftheIDT71T75702/902
to be suspended as long as necessary. All synchronous inputs are
ignored when
CENishighandtheinternaldeviceregisterswillholdtheir
previous values.
There are three chip enable pins (
CE1, CE2, CE2) that allow the
user to deselect the device when desired. If any one of these three is not
assertedwhenADV/
LDislow,nonewmemoryoperationcanbeinitiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state one cycle after the chip is deselected or a write
isinitiated.
The IDT71T75702/902 have an on-chip burst counter. In the burst
mode, the IDT71T75702/902 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the
LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/
LD signal is used to load a new
externaladdress(ADV/
LD=LOW)orincrementtheinternalburstcounter
(ADV/
LD = HIGH).
The IDT71T75702/902 SRAMs utilize IDT’s high-performance
CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm
100-pin plastic thin quad flatpack (TQFP) as well as a 119 ball grid array
(BGA).
Features
x
512K x 36, 1M x 18 memory configurations
x
Supports high performance system speed - 100 MHz
(7.5 ns Clock-to-Data Access)
x
ZBTTM Feature - No dead cycles between write and read cycles
x
Internally synchronized output buffer enable eliminates the
need to control
OE
x
Single R/
W
W (READ/WRITE) control pin
x
4-word burst capability (Interleaved or linear)
x
Individual byte write (
BW
BW1 - BW
BW
BW4) control (May tie active)
x
Three chip enables for simple depth expansion
x
2.5V power supply (±5%)
x
2.5V (±5%) I/O Supply (VDDQ)
x
Power down controlled by ZZ input
x
Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)
x
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA)
Description
The IDT71T75702/902 are 2.5V high-speed 18,874,368-bit
(18 Megabit) synchronous SRAMs organized as 512K x 36 /1M x 18.
They are designed to eliminate dead bus cycles when turning the bus
around between reads and writes, or writes and reads. Thus they have
been given the name ZBTTM, or Zero Bus Turnaround.
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock
cycle, and on the next clock cycle the associated data cycle occurs, be
it read or write.
IDT71T75702
IDT71T75902
512K x 36, 1M x 18
2.5V Synchronous ZBT SRAMs
2.5V I/O, Burst Counter
Flow-Through Outputs
相關(guān)PDF資料 |
PDF描述 |
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| IDT71V3576S133BQ | 128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect |
| IDT71V3576S133BQI | 128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect |
| IDT71V3576S133PFI | 128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT71T75902S75PF | 功能描述:IC SRAM 18MBIT 75NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 產(chǎn)品變化通告:Product Discontinuation 05/Nov/2008 標(biāo)準(zhǔn)包裝:84 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步 ZBT 存儲(chǔ)容量:4.5M（128K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:119-BGA 供應(yīng)商設(shè)備封裝:119-PBGA（14x22） 包裝:托盤 其它名稱:71V3557SA75BGI |
| IDT71T75902S75PF8 | 功能描述:IC SRAM 18MBIT 75NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 產(chǎn)品變化通告:Product Discontinuation 05/Nov/2008 標(biāo)準(zhǔn)包裝:84 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步 ZBT 存儲(chǔ)容量:4.5M（128K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:119-BGA 供應(yīng)商設(shè)備封裝:119-PBGA（14x22） 包裝:托盤 其它名稱:71V3557SA75BGI |
| IDT71T75902S75PFG | 功能描述:IC SRAM 18MBIT 75NS 100TQFP RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，異步 存儲(chǔ)容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
| IDT71T75902S75PFG8 | 功能描述:IC SRAM 18MBIT 75NS 100TQFP RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，異步 存儲(chǔ)容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
| IDT71T75902S75PFGI | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 18MBIT 7.5NS 100TQFP |
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