參數(shù)資料
型號(hào)： IDT70V639S12BFI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： HIGH-SPEED 3.3V 128K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM
中文描述： 128K X 18 DUAL-PORT SRAM, 12 ns, PBGA208
封裝： 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FPBGA-208
文件頁(yè)數(shù)： 12/23頁(yè)
文件大?。?/td> 187K
代理商： IDT70V639S12BFI
IDT70V639S
High-Speed 3.3V 128K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Preliminary
12
&.A.2%+-
W
,&
6D"
&.A.2%
CE
,&
6"
NOTES:
1. R/
W
or
CE
or
BE
n = V
IH
during all address transitions.
2. A write occurs during the overlap (t
EW
or t
WP
) of a
CE
= V
IL
and a R/
W
= V
IL
for memory array writing cycle.
3. t
WR
is measured fromthe earlier of
CE
or R/
W
(or
SEM
or R/
W
) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the
CE
or
SEM
= V
IL
transition occurs simultaneously with or after the R/
W
= V
IL
transition, the outputs remain in the High-impedance state.
6. Timng depends on which enable signal is asserted last,
CE
or R/
W
.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV fromsteady state with the Output Test Load
(Figure 2).
8. If
OE
= V
IL
during R/W controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to turn off and data to be
placed on the bus for the required t
DW
. If
OE
= V
IH
during an R/
W
controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified t
WP
.
9. To access RAM
CE
= V
IL
and
SEM
= V
IH
. To access semaphore,
CE
= V
IH
and
SEM
= V
IL
. t
EW
must be met for either condition.
R/
W
t
WC
t
HZ
t
AW
t
WR
t
AS
t
WP
DATA
OUT
(2)
t
WZ
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
(6)
(4)
(4)
(7)
UB
,
LB
5621 drw 08
(9)
CE
or
SEM
(9)
(7)
(3)
5621 drw 09
t
WC
t
AS
t
WR
t
DW
t
DH
ADDRESS
DATA
IN
R/
W
t
AW
t
EW
UB
,
LB
(3)
(2)
(6)
CE
or
SEM
(9)
(9)
相關(guān)PDF資料
PDF描述
IDT70V639S12PRF HIGH-SPEED 3.3V 128K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM
IDT70V639S12PRFI HIGH-SPEED 3.3V 128K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT70V639S12BFI8 功能描述:IC SRAM 2.25MBIT 12NS 208FBGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR)
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IDT70V639S12PRF8 功能描述:IC SRAM 2.25MBIT 12NS 128TQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR)
IDT70V639S12PRFI 功能描述:IC SRAM 2.25MBIT 12NS 128TQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR)
IDT70V639S12PRFI8 功能描述:IC SRAM 2.25MBIT 12NS 128TQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR)
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