參數(shù)資料
型號(hào)： IDT70T3339S166BC
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： JFET-Input Operational Amplifier 8-SOIC -40 to 85
中文描述： 512K X 18 DUAL-PORT SRAM, 12 ns, PBGA256
封裝： 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, BGA-256
文件頁(yè)數(shù)： 23/28頁(yè)
文件大小： 485K
代理商： IDT70T3339S166BC
6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
PRELIMINARY
Functional Description
The IDT70T3339/19/99 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide mnimal set-up and hold times
on address, data, and all critical control inputs. All internal registers are
clocked on the rising edge of the clock signal, however, the self-timed
internal write pulse width is independent of the cycle time.
An asynchronous output enable is provided to ease asyn-
chronous bus interfacing. Counter enable inputs are also provided to stall
the operation of the address counters for fast interleaved
memory applications.
CE
0
or a LOW on CE
1
for one clock cycle will power down
the internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT70T3339/19/99s for depth
expansion configurations. Two cycles are required with
CE
0
LOW and
CE
1
HIGH to re-activate the outputs.
Interrupts
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag (
INT
L
) is asserted when the right port writes to memory location
7FFFE (HEX), where a write is defined as
CE
R
= R/
W
R
= V
IL
per the
Truth Table. The left port clears the interrupt through access of
address location 7FFFE when
CE
L
= V
IL
and R/
W
L = V
IH
. Likewise, the
right port interrupt flag (
INT
R
) is asserted when the left
port writes to memory location 7FFFF (HEX) and to clear the interrupt
flag (
INT
R
), the right port must read the memory location 7FFFF (3FFFF
or 3FFFE for IDT70T3319 and 1FFFF or 1FFFE for IDT70T3399). The
message (18 bits) at 7FFFE or 7FFFF (3FFFF or 3FFFE for IDT70T3319
and 1FFFF or 1FFFE for IDT70T3399) is user-defined since it is an
addressable SRAMlocation. If the interrupt function is not used, address
locations 7FFFE and 7FFFF (3FFFF or 3FFFE for IDT70T3319 and
1FFFF or 1FFFE for IDT70T3399) are not used as mail boxes, but as
part of the randomaccess memory. Refer to Truth Table III for the interrupt
operation.
Collision Detection
Collision is defined as an overlap in access between the two ports
resulting in the potential for either reading or writing incorrect data to a
specific address. For the specific cases: (a) Both ports reading - no
data is corrupted, lost, or incorrectly output, so no collision flag is output
on either port. (b) One port writing, the other port reading - the end
result of the write will still be valid. However, the reading port mght
capture data that is in a state of transition and hence the reading port’s
collision flag is output. (c) Both ports writing - there is a risk that the two
ports will interfere with each other, and the data stored in memory will
not be a valid write fromeither port (it may essentially be a random
combination of the two). Therefore, the collision flag is output on both
ports. Please refer to Truth Table IV for all of the above cases.
The alert flag
(
COL
) is asserted on the 2nd or 3rd rising clock
edge of the affected port following the collision, and remains low for
one cycle. Please refer to Collision DetectionTimng table on Page 21.
During that next cycle, the internal arbitration is engaged in resetting
the alert flag (this avoids a specific requirement on the part of the user
to reset the alert flag). If two collisions occur on subsequent clock
cycles, the second collision may not generate the appropriate alert
Sleep Mode
The IDT70T3339/19/99 is equipped with an optional sleep or low
power mode on both ports. The sleep mode pin on both ports is
asynchronous and active high. During normal operation, the ZZ pin is
pulled low. When ZZ is pulled high, the port will enter sleep mode where
it will meet lowest possible power conditions. The sleep mode timng
diagramshows the modes of operation: Normal Operation, No Read/Write
Allowed and Sleep Mode.
For normal operation all inputs must meet setup and hold times prior
to sleep and after recovering fromsleep. Clocks must also meet cycle high
and low times during these periods. Three cycles prior to asserting ZZ
(ZZx = V
IH
) and three cycles after de-asserting ZZ (ZZx = V
IL
), new reads
or writes are not allowed. If a write or read operation occurs during these
periods, the memory array may be corrupted. Validity of data out fromthe
RAMcannot be guaranteed immediately after ZZ is asserted (prior to being
in sleep).
During sleep mode the RAMautomatically deselects itself. The RAM
disconnects its internal clock buffer. The external clock may continue to run
without impacting the RAMs sleep current (I
ZZ
). All outputs will remain in
high-Z state while in sleep mode. All inputs are allowed to toggle. The RAM
will not be selected and will not performany reads or writes.
Collision detection on the IDT70T3339/19/99 represents a
significant advance in functionality over current sync multi-ports, which
have no such capability. In addition to this functionality the
IDT70T3339/19/99 sustains the key features of bandwidth and
flexibility. The collision detection function is very useful in the case of
bursting data, or a string of accesses made to sequential addresses, in
that it indicates a problemwithin the burst, giving the user the option of
either repeating the burst or continuing to watch the alert flag to see
whether the number of collisions increases above an acceptable
threshold value. Offering this function on chip also allows users to
reduce their need for arbitration circuits, typically done in CPLD’s or
FPGA’s. This reduces board space and design complexity, and gives
the user more flexibility in developing a solution.
flag. A third collision will generate the alert flag as appropriate. In the
event that a user initiates a burst access on both ports with the same
starting address on both ports and one or both ports writing during
each access (i.e., imposes a long string of collisions on contiguous
clock cycles), the alert flag will be asserted and cleared every other
cycle. Please refer to the Collision Detection timng waveformon page
21.
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參數(shù)描述
IDT70T3339S166BC8 功能描述:IC SRAM 9MBIT 166MHZ 256BGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR)
IDT70T3339S166BF 功能描述:IC SRAM 9MBIT 166MHZ 208FBGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR)
IDT70T3339S166BF8 功能描述:IC SRAM 9MBIT 166MHZ 208FBGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR)
IDT70T3339S200BC 功能描述:IC SRAM 9MBIT 200MHZ 256BGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR)
IDT70T3339S200BC8 功能描述:IC SRAM 9MBIT 200MHZ 256BGA RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR)
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