參數(shù)資料
型號(hào): IDT70T3339S166BC
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: JFET-Input Operational Amplifier 8-SOIC -40 to 85
中文描述: 512K X 18 DUAL-PORT SRAM, 12 ns, PBGA256
封裝: 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, BGA-256
文件頁(yè)數(shù): 19/28頁(yè)
文件大小: 485K
代理商: IDT70T3339S166BC
6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
PRELIMINARY
Timing Waveform of Write with Address Counter Advance
(Flow-through or Pipelined Inputs)
(1)
Timing Waveform of Counter Repeat
(2)
NOTES:
1.
CE
0
,
UB
,
LB
, and R/
W
= V
IL
; CE
1
and
REPEAT
= V
IH
.
2.
CE
0
,
UB
,
LB
= V
IL
; CE
1
= V
IH
.
3. The "Internal Address" is equal to the "External Address" when
ADS
= V
IL
and equals the counter output when
ADS
= V
IH
.
4. Addresses do not have to be accessed sequentially since
ADS
= V
IL
constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
5. Output state (High, Low, or High-impedance) is determned by the previous cycle control signals.
6. No dead cycle exists during
REPEAT
operation. A READ or WRITE cycle may be coincidental with the counter
REPEAT
cycle: Address loaded by last valid
ADS
load will be accessed. Extra cycles are shown here simply for clarification. For more information on
REPEAT
function refer to Truth Table II.
7.
CNTEN
= V
IL
advances Internal Address from‘An to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
ADDRESS
An
CLK
DATA
IN
Dn
Dn + 1
Dn + 1
Dn + 2
ADS
CNTEN
t
CH2
t
CL2
t
CYC2
5652 drw 17
INTERNAL
(3)
ADDRESS
An
(7)
An + 1
An + 2
An + 3
An + 4
Dn + 3
Dn + 4
t
SA
t
HA
t
SAD
t
HAD
WRITE
COUNTER HOLD
WRITE WITH COUNTER
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
t
SD
t
HD
t
SCN
t
HC
N
,
ADDRESS
An
D
0
t
CH2
t
CL2
t
CYC2
Q
LAST
Q
LAST+1
LAST
ADS
LOAD
CLK
DATA
IN
R/
W
REPEAT
5652 drw 18
INTERNAL
(3)
ADDRESS
ADS
CNTEN
t
SRPT
t
HRPT
t
SD
t
HD
t
SW
t
HW
EXECUTE
REPEAT
WRITE
LAST
ADS
ADDRESS
READ
LAST
ADS
ADDRESS
READ
LAST
ADS
ADDRESS + 1
READ
ADDRESS n
Qn
An + 1
An + 2
READ
ADDRESS n+1
DATA
OUT
t
SA
t
HA
LAST
ADS
+1
An
An + 1
(4)
(5)
(6)
Ax
t
SAD
t
HAD
t
SCN
t
HCN
,
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