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參數(shù)資料
| 型號： | IDT70T3319S133BC |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 2.5V 512/256/128K X 18 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| 中文描述： | 256K X 18 DUAL-PORT SRAM, 15 ns, PBGA256 |
| 封裝： | 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, BGA-256 |
| 文件頁數(shù)： | 15/28頁 |
| 文件大?。?/td> | 485K |
| 代理商： | IDT70T3319S133BC |
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6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
PRELIMINARY
Timing Waveform of Left Port Write to Pipelined Right Port Read
(1,2,4)
Timing Waveform with Port-to-Port Flow-Through Read
(1,2,4)
NOTES:
1.
CE
0
,
UB
,
LB
, and
ADS
= V
IL
; CE
1
,
CNTEN
, and
REPEAT
= V
IH
.
2.
OE
= V
IL
for the Right Port, which is being read from
OE
= V
IH
for the Left Port, which is being written to.
3. If t
CO
< mnimumspecified, then data fromPort "B" read is not valid until following Port "B" clock cycle (i.e., time fromwrite to valid read on opposite port will be
t
CO
+ t
CYC
+ t
CD1
). If t
CO
> mnimum then data fromPort "B" read is available on first Port "B" clock cycle (i.e., time fromwrite to valid read on opposite port will
be t
CO
+ t
CD1
).
4. All timng is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
CLK
"A"
R/
W
"A
"
ADDRESS
"A"
DATA
IN"A"
CLK
"B"
R/
W
"B"
ADDRESS
"B"
DATA
OUT"B"
t
SW
t
HW
t
SA
t
HA
t
SD
t
HD
t
SW
t
HW
t
SA
t
HA
t
CO
(3)
t
CD2
MNO
VALID
NO
H
MATC
H
MATC
H
VALID
5652 drw 09
t
DC
,
DATA
IN "A"
CLK
"B"
R/
W
"B"
ADDRESS
"A"
R/
W
"A"
CLK
"A"
ADDRESS
"B"
NO
MATCH
MATCH
NO
MATCH
MATCH
VALID
t
CD1
t
DC
DATA
OUT "B"
5652 drw 10
VALID
VALID
t
SW
t
HW
t
SA
t
HA
t
SD
t
HD
t
HW
t
HA
t
CD1
t
CO
t
DC
t
SA
t
SW
(3)
,
NOTES:
1.
CE
0
,
UB
,
LB
, and
ADS
= V
IL
; CE
1
,
CNTEN
, and
REPEAT
= V
IH
.
2.
OE
= V
IL
for Port "B", which is being read from
OE
= V
IH
for Port "A", which is being written to.
3. If t
CO
< mnimumspecified, then data fromPort "B" read is not valid until following Port "B" clock cycle (ie, time fromwrite to valid read on opposite port will be
t
CO
+ 2 t
CYC2
+ t
CD2
). If t
CO
> mnimum then data fromPort "B" read is available on first Port "B" clock cycle (ie, time fromwrite to valid read on opposite port
will be t
CO
+ t
CYC2
+ t
CD2
).
4. All timng is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT70T3319S133BC8 | 功能描述:IC SRAM 4MBIT 133MHZ 256BGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR) |
| IDT70T3319S133BCI | 功能描述:IC SRAM 4MBIT 133MHZ 256BGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR) |
| IDT70T3319S133BCI8 | 功能描述:IC SRAM 4MBIT 133MHZ 256BGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR) |
| IDT70T3319S133BF | 功能描述:IC SRAM 4MBIT 133MHZ 208FBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR) |
| IDT70T3319S133BF8 | 功能描述:IC SRAM 4MBIT 133MHZ 208FBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:8K (1K x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:1.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR) |
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