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參數資料
| 型號： | IDT70825L35G |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAM⑩) |
| 中文描述： | 8K X 16 STANDARD SRAM, 35 ns, CPGA84 |
| 封裝： | PGA-84 |
| 文件頁數： | 10/21頁 |
| 文件大?。?/td> | 319K |
| 代理商： | IDT70825L35G |
6.31
10
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
FLOW CONTROL REGISTER DESCRIPTION
(1,2)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Flag Status Bit 0, (Bit 1)
0
1
Functional Description
Clears Buffer Flag
EOB
1
, (
EOB
2
).
No change to the Buffer Flag.
(2)
NOTES:
1. Either bit 0 or bit 1, or both bits, may be changed simultaneously. One may be cleared while the second is left alone or cleared.
2. Remains as it was prior to the
CMD
operation, either HIGH (1) or LOW (0).
3016 tbl 18
End of buffer flag for Buffer #1
End of buffer flag for Buffer #2
15
0
MSB
H
H
H
H
H
H
H
H
H
H
H
H
H
1
0
LSB I/O BITS
H
3016 drw 12
NOTE:
1. "H" = V
OH
for I/O in the output state and "Don't Cares" for I/O in the input state.
Buffer #1 flow control
Buffer #2 flow control
Counter Release
(STOP Mode Only)
15
MSB
LSB I/O BITS
0
H
H
H
H
H
H
H
4
3
2
1
0
H
H
H
H
3016 drw 11
CASES 6 AND 7: FLAG STATUS REGISTER BIT DESCRIPTION
(1)
3016 tbl 17
FLOW CONTROL BITS
Flow Control Bits
Bit 1 & Bit 0
(Bit 3 & Bit 2)
00
Mode
Functional Description
BUFFER
CHAINING
STOP
EOB
1
(
EOB
2
) is asserted (Active Low output) when the pointer matches the end address of Buffer
#1 (Buffer #2). The pointer value is changed to the start address of Buffer #2 (Buffer #1).
(1,3)
EOB
1
(
EOB
2
) is asserted when the pointer matches the end address of Buffer #1 (Buffer #2).
The address pointer will stop incrementing when it reaches the next address (
EOB
address + 1), if
CNTEN
is Low on the next clock's rising edge. Otherwise, the address pointer will stop incrementing on
EOB
. Sequential write operations are inhibited after the address pointer is stopped. The pointer can be
released by bit 4 of the flow control register.
(1,2,4)
EOB
1
(
EOB
2
) is asserted when the pointer matches the end address of Buffer #1 (Buffer #2).
The pointer keeps incrementing for further operations.
(1)
EOB
1
(
EOB
2
) is not asserted when the pointer reaches the end address of Buffer #1 (Buffer #2),
although the flag status bits will be set. The pointer keeps incrementing for further operations.
01
10
LINEAR
11
MASK
NOTES:
1.
EOB
1
and
EOB
2
may be asserted (set) at the same time, if both end addresses have been loaded with the same value.
2.
CMD
Flow Control bits are unchanged, the count does not continue advancement.
3. If
EOB
1
and
EOB
2
are equal, then the pointer will jump to the start of Buffer #1.
4. If counter has stopped at EOBx and was released by bit 4 of the flow control register,
CNTEN
must be LOW on the next rising edge of SCLK otherwise
the flow control will remain in the STOP mode.
CASE 6: FLAG STATUS REGISTER WRITE CONDITIONS
(1)
3016 tbl 19
Flag Status Bit 0, (Bit 1) Functional Description
0
EOB
1
(
EOB
2
) flag has not been set, the
Pointer has not reached the End of the
Buffer.
EOB
1
(
EOB
2
) flag has been set, the
Pointer has reached the End of the Buffer.
1
CASE 7: FLAG STATUS REGISTER READ CONDITIONS
NOTES:
1. "H" = V
OH
for I/O in the output state and "Don't Cares"' for I/O in the input state.
2. Writing a 0 into bit 4 releases the address pointer after it is stopped due to the STOP mode and allows sequential write operations to resume. This occurs
asynchronously of SCLK, and therefore caution should be taken. The pointer will be at address EOB+2 on the next rising edge of SCLK that is enabled
by
CNTEN
. The pointer is also released by
RST
,
SLD
,
SSTRT
1 and
SSTRT
2 operations.
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