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| 型號(hào)： | IDT70121L55JG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
| 中文描述： | 2K X 9 DUAL-PORT SRAM, 55 ns, PQCC52 |
| 封裝： | 0.75 X 0.75 INCH, 0.17 INCH HEIGHT, GREEN, PLASTIC, LCC-52 |
| 文件頁(yè)數(shù)： | 5/15頁(yè) |
| 文件大?。?/td> | 139K |
| 代理商： | IDT70121L55JG |
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5
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
APRIL 05, 2006
Data Retention Charac teristic s
(L V ersion Only)
Data Retention Waveform
AC Test Conditions
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(For t
LZ
, t
HZ
, t
WZ
, t
OW
)
*Including scope and jig.
NOTES:
1. V
CC
= 2V, T
A
= +25°C, and are not production tested.
2. t
RC
= Read Cycle Time.
3. This parameter is guaranteed but is not production tested.
V
DR
2V
≥
DATA RETENTION MODE
Vcc
CE
4.5V
t
CDR
t
R
V
IH
V
DR
V
IH
4.5V
2654 drw 03
1250
30pF
775
DATA
OUT
BUSY
INT
5V
5V
1250
5pF*
775
DATA
OUT
2654 drw 04
Symbol
Parameter
Test Condition
Mn.
Typ.
(1)
Max.
Unit
V
DR
V
CC
for Data Retention
2.0
___
___
V
I
CCDR
Data Retention Current
V
CC
= 2V,
CE
> V
CC
- 0.2V
IND.
___
100
4000
μA
t
CDR
(3)
Chip Deselect to Data Retention Time
V
IN
> V
CC
- 0.2V or V
IN
< 0.2
COML.
___
100
1500
t
R
(3)
Operation Recovery Time
t
RC
(2)
___
___
V
2654 tbl 07
Input Pulse Levels
Input Rise/Fall Times
Input Timng Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
Figures 1 and 2
2654 tbl 08
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT70121L55JGI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
| IDT70121L55L52 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
| IDT70121L55L52B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
| IDT70121L70L52B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
| IDT70121S | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
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