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參數(shù)資料
| 型號(hào)： | IDT70121L45JG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
| 中文描述： | 2K X 9 DUAL-PORT SRAM, 45 ns, PQCC52 |
| 封裝： | 0.75 X 0.75 INCH, 0.17 INCH HEIGHT, GREEN, PLASTIC, LCC-52 |
| 文件頁數(shù)： | 14/15頁 |
| 文件大?。?/td> | 139K |
| 代理商： | IDT70121L45JG |
6.42
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
Functional Description
The IDT70121/125 provides two ports with separate control, address
and I/O pins that permt independent access for reads or writes to any
location in memory. The IDT70121/125 has an automatic power down
feature controlled by
CE
. The
CE
controls on-chip power down circuitry
that permts the respective port to go into a standby mode when not selected
(
CE
HIGH). When a port is enabled, access to the entire memory array
is permtted.
APRIL 05, 2006
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(
INT
L
) is asserted when the right port writes to memory location 7FE
(HEX), where a write is defined as the
CE
= R/
W
= V
IL
per Truth Table
II. The left port clears the interrupt by access address location 7FE access
when
CE
R
=
OE
R
= V
IL
, R/
W
is a "don't care". Likewise, the right port
interrupt flag (INT
R
) is asserted when the left port writes to memory location
7FF (HEX) and to clear the interrupt flag (INT
R
), the right port must access
the memory location 7FF. The message (9 bits) at 7FE or 7FF is user-
defined, since it is an addressable SRAMlocation. If the interrupt function
is not used, address locations 7FE and 7FF are not used as mail boxes,
but as part of the randomaccess memory. Refer to Table II for the interrupt
operation.
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAMis “busy”.
The
BUSY
pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a
BUSY
indication, the write signal is gated internally
to prevent the write fromproceeding.
The use of
BUSY
logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the
BUSY
outputs together
and use any
BUSY
indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of
BUSY
logic is
not desirable, the
BUSY
logic can be disabled by using the IDT70125
(SLAVE). In the IDT70125, the
BUSY
pin operates solely as a write inhibit
input pin. Normal operation can be programmed by tying the
BUSY
pins
HIGH. Once in slave mode the
BUSY
pin operates solely as a write inhibit
input pin. If desired, unintended write operations can be prevented to a
port by tying the
BUSY
pin for that port LOW.
The
BUSY
outputs on the IDT70121/125 RAMin master mode, are
push-pull type outputs and do not require pull up resistors to operate. If
these RAMs are being expanded in depth, then the
BUSY
indication for
the resulting array requires the use of an external AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an IDT70121/125 RAMarray in width while using
BUSY
logic, one master part is used to decide which side of the RAMarray
will receive a
BUSY
indication, and to output that indication. Any number
of slaves to be addressed in the same address range as the master use
the
BUSY
signal as a write inhibit signal. Thus on the IDT70121 RAMthe
BUSY
pin is an output of the part, and the BUSY pin is an input of the
IDT70125 as shown in Figure 3.
If two or more master parts were used when expanding in width, a split
decision could result with one master indicating
BUSY
on one side of the
array and another master indicating
BUSY
on one other side of the array.
This would inhibit the write operations fromone port for part of a word and
Figure 3. Busy and chip enable routing for both width and depth
expansion with 70121 (Master) and 70125 (Slave) RAMs.
2654 drw 14
MASTER
Dual Port
RAM
BUSY
L
BUSY
R
CE
MASTER
Dual Port
RAM
BUSY
L
BUSY
R
CE
SLAVE
Dual Port
RAM
BUSY
L
BUSY
R
CE
SLAVE
Dual Port
RAM
BUSY
L
BUSY
R
CE
BUSY
L
BUSY
R
D
,
inhibit the write operations fromthe other port for the other part of the word.
The
BUSY
arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a
BUSY
flag to be output fromthe master before the actual write
pulse can be initiated with either the R/
W
signal or the byte enables. Failure
to observe this timng can result in a glitched internal write inhibit signal and
corrupted data in the slave.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT70121L45JGI | HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
| IDT70121L55JG | HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
| IDT70121L55JGI | HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
| IDT70121S25JG | HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
| IDT70121S25JGI | Replacement for Harris part number ICL7660SMTV/883B. Buy from authorized manufacturer Rochester Electronics. |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT70121L45JGI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT |
| IDT70121L45L52 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
| IDT70121L45L52B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
| IDT70121L55J | 功能描述:IC SRAM 18KBIT 55NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:MoBL® 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 異步 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR) |
| IDT70121L55J8 | 功能描述:IC SRAM 18KBIT 55NS 52PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:MoBL® 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 異步 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:45ns 接口:并聯(lián) 電源電壓:2.2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFBGA 供應(yīng)商設(shè)備封裝:48-VFBGA（6x8） 包裝:帶卷 (TR) |
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