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參數(shù)資料
| 型號(hào)： | IDT7009L20PFI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | USBF TV Field Memory Key 2048MB RAM Nickel RoHS Compliant: Yes |
| 中文描述： | 128K X 8 DUAL-PORT SRAM, 20 ns, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100 |
| 文件頁(yè)數(shù)： | 7/17頁(yè) |
| 文件大小： | 143K |
| 代理商： | IDT7009L20PFI |
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6.42
IDT7009L
High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
85.<5
.$23/4
'#
NOTES:
1. Transition is measured 0mV fromLow or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranted by device characterization, but is not production tested.
3. To access RAM
CE
= V
IL
and
SEM
= V
IH
. To access semaphore,
CE
= V
IH
and
SEM
= V
IL
. Either condition must be valid for the entire t
EW
time.
4. The specification for t
DH
must be met by the device supplying write data to the RAMunder all operating conditions. Although t
DH
and t
OW
values will vary over voltage
and temperature, the actual t
DH
will always be smaller than the actual t
OW
.
5. Industrial Temperature: for specific speeds, packages and powers contact your sales office.
85.<5
.$23/4
'#
7009L15
Com'l Only
7009L20
Com'l Only
Unit
Symbol
Parameter
Min.
Max.
Min.
Max.
READ CYCLE
t
RC
Read Cycle Time
15
____
20
____
ns
t
AA
Address Access Time
____
15
____
20
ns
t
ACE
Chip Enable Access Time
(4)
____
15
____
20
ns
t
AOE
Output Enable Access Time
____
10
____
12
ns
t
OH
Output Hold fromAddress Change
3
____
3
____
ns
t
LZ
Output Low-Z Time
(1,2)
3
____
3
____
ns
t
HZ
Output High-Z Time
(1,2)
____
10
____
10
ns
t
PU
Chip Enable to Power Up Time
(2)
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(2)
____
15
____
20
ns
t
SOP
Semaphore Flag Update Pulse (
OE
or
SEM
)
10
____
10
____
ns
t
SAA
Semaphore Address Access Time
____
15
____
20
ns
4839 tbl 12
Symbol
Parameter
7009L15
Com'l Only
7009L20
Com'l Only
Unit
Min.
Max.
Min.
Max.
WRITE CYCLE
t
WC
Write Cycle Time
15
____
20
____
ns
t
EW
Chip Enable to End-of-Write
(3)
12
____
15
____
ns
t
AW
Address Valid to End-of-Write
12
____
15
____
ns
t
AS
Address Set-up Time
(3)
0
____
0
____
ns
t
WP
Write Pulse Width
12
____
15
____
ns
t
WR
Write Recovery Time
0
____
0
____
ns
t
DW
Data Valid to End-of-Write
10
____
15
____
ns
t
HZ
Output High-Z Time
(1,2)
____
10
____
10
ns
t
DH
Data Hold Time
(4)
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
10
____
10
ns
t
OW
Output Active fromEnd-of-Write
(1,2,4)
0
____
0
____
ns
t
SWRD
SEM
Flag Write to Read Time
5
____
5
____
ns
t
SPS
SEM
Flag Contention Window
5
____
5
____
ns
4839 tbl 13
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相關(guān)代理商/技術(shù)參數(shù) |
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| IDT7009L20PFI8 | 功能描述:IC SRAM 1MBIT 20NS 100TQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，同步 存儲(chǔ)容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
| IDT70101L25J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
| IDT70101L25L52 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
| IDT70101L35J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
| IDT70101L35L52 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Dual-Port SRAM |
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