參數(shù)資料
型號(hào): IDT7009L20PFI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: USBF TV Field Memory Key 2048MB RAM Nickel RoHS Compliant: Yes
中文描述: 128K X 8 DUAL-PORT SRAM, 20 ns, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
文件頁(yè)數(shù): 10/17頁(yè)
文件大?。?/td> 143K
代理商: IDT7009L20PFI
10
IDT7009L
High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
NOTES:
1. Port-to-port delay through RAMcells fromwriting port to reading port, refer to "Timng Waveformof Write with Port-to-Port Read and
BUSY
(M/
S
= V
IH
)".
2. To ensure that the earlier of the two ports wins.
3. t
BDD
is a calculated parameter and is the greater of 0, t
WDD
t
WP
(actual) or t
DDD
t
DW
(actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. Industrial Temperature: for specific speeds, packages and powers contact your sales office.
85.<5
.$23/4
#
7009L15
Com'l Only
7009L20
Com'l Only
Symbol
Parameter
Mn.
Max.
Mn.
Max.
Unit
BUSY
TIMING (M/
S
=V
IH
)
t
BAA
BUSY
Access Time fromAddress Match
____
15
____
20
ns
t
BDA
BUSY
Disable Time fromAddress Not Matched
____
15
____
20
ns
t
BAC
BUSY
Access Time fromChip Enable Low
____
15
____
20
ns
t
BDC
BUSY
Access Time fromChip Enable High
____
15
____
17
ns
t
APS
Arbitration Priority Set-up Time
(2)
5
____
5
____
ns
t
BDD
BUSY
Disable to Valid Data
(3)
____
15
____
17
ns
t
WH
Write Hold After
BUSY
(5)
12
____
15
____
ns
BUSY
TIMING (M/
S
=V
IL
)
t
WB
BUSY
Input to Write
(4)
0
____
0
____
ns
t
WH
Write Hold After
BUSY
(5)
12
____
15
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1)
____
30
____
45
ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
25
____
30
ns
4839 tbl 14
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