參數(shù)資料
型號: IDT5V49EE901NLGI8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 7/36頁
文件大小: 0K
描述: IC PLL CLK GEN 200MHZ 32VFQFN
產(chǎn)品培訓(xùn)模塊: VersaClock™ III Programmable Clocks
特色產(chǎn)品: VersaClock III Timing Devices
標(biāo)準(zhǔn)包裝: 2,500
系列: VersaClock™ III
類型: 時鐘發(fā)生器,多路復(fù)用器
PLL: 帶旁路
輸入: LVCMOS,LVTTL,晶體
輸出: HCSL,LVCMOS,LVDS,LVPECL,LVTTL
電路數(shù): 1
比率 - 輸入:輸出: 2:9
差分 - 輸入:輸出: 無/是
頻率 - 最大: 500MHz
除法器/乘法器: 是/是
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-VFQFPN 裸露焊盤(4x4)
包裝: 帶卷 (TR)
IDT5V49EE901
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
IDT EEPROM PROGRAMMABLE CLOCK GENERATOR
15
IDT5V49EE901
REV R 092412
Progrestore
EEPROM Interface
The IDT5V49EE901 can also store its configuration in an
internal EEPROM. The contents of the device's internal
programming registers can be saved to the EEPROM by
issuing a save instruction (ProgSave) and can be loaded
back to the internal programming registers by issuing a
restore instruction (ProgRestore).
To initiate a save or restore using I2C, only two bytes are
transferred. The Device Address is issued with the
read/write bit set to “0”, followed by the appropriate
command code. The save or restore instruction executes
after the STOP condition is issued by the Master, during
which time the IDT5V49EE901 will not generate
Acknowledge bits. The IDT5V49EE901 will acknowledge
the instructions after it has completed execution of them.
During that time, the I2C bus should be interpreted as busy
by all other users of the bus.
On power-up of the IDT5V49EE901, an automatic restore is
performed to load the EEPROM contents into the internal
programming registers. The IDT5V49EE901 will be ready to
accept a programming instruction once it acknowledges its
7-bit I2C address.
SAddress
R/W
ACK
Command Code
ACK
P
7-bits
0
1-bit
8-bits: xxxx xx10
1-bit
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