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參數(shù)資料
| 型號： | IDT5V49EE901NLGI8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 29/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLK GEN 200MHZ 32VFQFN |
| 產(chǎn)品培訓(xùn)模塊： | VersaClock™ III Programmable Clocks |
| 特色產(chǎn)品： | VersaClock III Timing Devices |
| 標準包裝： | 2,500 |
| 系列： | VersaClock™ III |
| 類型： | 時鐘發(fā)生器，多路復(fù)用器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVTTL，晶體 |
| 輸出： | HCSL，LVCMOS，LVDS，LVPECL，LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:9 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 500MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-VFQFPN 裸露焊盤（4x4） |
| 包裝： | 帶卷 (TR) |
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IDT5V49EE901
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
IDT EEPROM PROGRAMMABLE CLOCK GENERATOR
35
IDT5V49EE901
REV R 092412
Revision History
Rev.
Originator
Date
Description of Change
A
R.Willner
4/22/09
Advance Information.
B
R.Willner
5/04/09
Identified VDDX (crystal oscillator power) and AVDD (analog power) on device.
C
R.Willner
6/04/09
Add default configurations, pull-down resistor values on input pins.
Released Datasheet from Advanced Information.
D
R.Willner
06/10/09
Updates: crystal load specs; “Output Duty Cycle” specs; addresses 0x07, 0x02 and 0xBF
in “Programming Registers” table.
E
R.Willner
7/21/09
Corrected 32VFQFPN marking to be consistant with manufacturing.
F
R.Willner
08/26/09
Updated 32-pin VFQFPN thermal data
G
R.Willner
10/05/09
Changed IP3[3:0] to IP3[4:0] ; updated “Programming Registers Table”.
H
R.Willner
12/07/09
Updated VDD min/max specs in Recommended Operation Conditions
I
R.Willner
12/09/09
Increased max VCO frequency to 1300 MHz.
J
R.Willner
02/23/10
Updated Recommended Operation Conditions to include Vddx and AVdd parameters.
K
R.Willner
04/22/11
Added Landing Pattern diagram for 32QFN.
L
A. Tsui
07/07/11
Updated package dimension drawing
M
R. Willner
12/6/11
Correct pin description.
N
R. Willner
04/17/12
1. Change description for SDAT and SCLK pins.
2. Add new footnotes to pin descriptions table
3. Added section "Crystal Clock Selection"
4. Added logic diagram and Truth table for "SD/OE Pin Function" section.
5. Corrected register readback values for 0x52~0x54 and 0x7C~0x7F.
6. Update to QFN package drawing - exposed thermal pad callout.
P
A. Tsui
06/01/12
1. Updated SD-OE pin description; from (Default is active HIGH) to (Default is active
LOW)
2. Updated “OUTn” column in Truth Table with “High-Z” specs and added footnote 2,
“High-Z regardless of OEM bits”.
3. Updated “SD-OE Pin Function” section to reflect that SP is “0”changed from active
HIGH to active LOW, and SP is “1” changed from active LOW to active HIGH.
Q
R.Willner
06/18/12
Added Min/Max spread values to "Spread Spectrum Generation Specifications" table;
fMOD - Max. 120kHz; Down Spread - Min. -0.5%, Max. -4.0%; Center Spread - Min.
±0.25%, Max. ±2.0%
R
R.Willner
09/24/12
Change differential outputs from 5pF loads to 2pF loads so that they are consistent with
the industry. Capacitive loads were also added to the test circuit diagrams for HCSL
outputs. Slew Rate (t4) Output Load test conditions were also changed from 15pF to 5pF.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT5V49EE901PGGI | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GENERATOR |
| IDT5V49EE901PGGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLK GEN EEPROM PROGR 28TSSOP |
| IDT5V49EE902-EVB | 制造商:Integrated Device Technology Inc 功能描述:EVAL BOARD FOR IDT 5V49EE902 |
| IDT5V49EE902NLGI | 功能描述:IC CLOCK GEN PLL 500MHZ 32VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| IDT5V49EE902NLGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLK GEN EEPROM PROGR 32QFN |
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