參數(shù)資料
型號： IDT5V49EE901NLGI8
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 6/36頁
文件大?。?/td> 0K
描述： IC PLL CLK GEN 200MHZ 32VFQFN
產(chǎn)品培訓(xùn)模塊： VersaClock™ III Programmable Clocks
特色產(chǎn)品： VersaClock III Timing Devices
標(biāo)準(zhǔn)包裝： 2,500
系列： VersaClock™ III
類型： 時鐘發(fā)生器，多路復(fù)用器
PLL： 帶旁路
輸入： LVCMOS，LVTTL，晶體
輸出： HCSL，LVCMOS，LVDS，LVPECL，LVTTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:9
差分 - 輸入:輸出： 無/是
頻率 - 最大： 500MHz
除法器/乘法器： 是/是
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 32-VFQFPN 裸露焊盤（4x4）
包裝： 帶卷 (TR)
IDT5V49EE901
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
IDT EEPROM PROGRAMMABLE CLOCK GENERATOR
14
IDT5V49EE901
REV R 092412
External I2C Interface Condition
Progwrite
Progwrite Command Frame
Writes can continue as long as a Stop condition is not sent and each byte will increment the register address.
Progread
Note: If the expected read command is not from the next higher register to the previous read or write command, then set a
known “read” register address prior to a read operation by issuing the following command:
Prior to Progread Command Set Register Address
The user can ignore the STOP condition above and use a repeated START condition instead, straight after the slave
acknowledgement bit (i.e., followed by the Progread command):
Progread Command Frame
Progsave
Note:
PROGWRITE is for writing to the IDT5V49EE901 registers.
PROGREAD is for reading the IDT5V49EE901 registers.
PROGSAVE is for saving all the contents of the IDT5V49EE901 registers to the EEPROM.
PROGRESTORE is for loading the entire EEPROM contents to the IDT5V49EE901 registers.
SAddress
R/W
ACK
Command Code
ACK
Register
ACK
Data
ACK
P
7-bits
0
1-bit
8-bits: xxxx xx00
1-bit
8-bits
1-bit
8-bits
1-bit
SAddress
R/W
ACK
Command Code
ACK
Register
ACK
P
7-bits
0
1-bit
8-bits: xxxx xx00
1-bit
8-bits
1-bit
SAddress
R/W
ACK
ID Byte
ACK
Data_1
ACK
Data_2
ACK
Data_last
NACK
P
7-bits
1
1-bit
8-bits
1-bit
8-bits
1-bit
8-bits
1-bit
8-bits
1-bit
SAddress
R/W
ACK
Command Code
ACK
P
7-bits
0
1-bit
8-bits: xxxx xx01
1-bit
KEY:
From Master to Slave
From Master to Slave, but can be omitted if followed by the correct sequence
Normally, data transfer is terminated by a STOP condition generated by the Master. However, if the Master still wishes to communicate on the bus, it can
generate a separate START condition, and address another Slave address without first generating a STOP condition.
From Slave to Master
SYMBOLS:
ACK - Acknowledge (SDAT LOW)
NACK – Not Acknowledge (SDAT HIGH)
SR – Repeated Start Condition
S – START Condition
P – STOP Condition
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT5V49EE901PGGI 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GENERATOR
IDT5V49EE901PGGI8 制造商:Integrated Device Technology Inc 功能描述:IC CLK GEN EEPROM PROGR 28TSSOP
IDT5V49EE902-EVB 制造商:Integrated Device Technology Inc 功能描述:EVAL BOARD FOR IDT 5V49EE902
IDT5V49EE902NLGI 功能描述:IC CLOCK GEN PLL 500MHZ 32VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT
IDT5V49EE902NLGI8 制造商:Integrated Device Technology Inc 功能描述:IC CLK GEN EEPROM PROGR 32QFN
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