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參數(shù)資料
| 型號： | IDT5V2528APGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 2.5V / 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER |
| 中文描述： | 5V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | TSSOP-28 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大小： | 61K |
| 代理商： | IDT5V2528APGI |
5
INDUSTRIAL TEMPERATURE RANGE
IDT5V2528/A
2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER
INPUT TIMING REQUIREMENTS OV ER OPERATING RANGE
5V2528
5V2528A
Mn
25
40%
Max
140
60%
1
Mn
25
40%
Max
167
60%
1
Units
MHz
f
CLOCK
Clock frequency
Input clock duty cycle
Stabilization time
(1)
t
LOCK
ms
NOTE:
1.Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference
signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew and jitter parameters given in the switching characteristics table are
not applicable.
NOTES:
1. All parameters are measured with the following load conditions: 30pF ||500
for 3.3V outputs and 20pF ||500
for 2.5V outputs.
2. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
3. Phase error does not include jitter.
4. All skew parameters are only valid for equal loading of all outputs.
5. Measured for V
DDQ
= 2.3V and 3V, 2.5V and 3.3V, or 2.7V and 3.6V.
SWITCHING CHARACTERISTICS OV ER OPERATING RANGE - 5V 2528
(1)
Symbol
t
PHASE
error
t
PHASE
error - jitter
(3)
t
SK
1(0)
(4)
t
SK
2(0)
(4)
t
SK
3(0)
(4,5)
t
J
Parameter
(2)
Min.
–
150
–
50
—
—
—
–
75
45
0.8
0.8
0.5
0.5
Typ.
—
—
—
—
—
—
—
—
—
—
—
Max.
150
50
150
150
200
75
55
2.1
2.1
1.5
1.5
Unit
ps
ps
ps
ps
ps
ps
%
ns
ns
ns
ns
Phase Error fromRising Edge CLK to Rising Edge FBIN (100MHz-133MHz)
Phase Error mnus Jitter fromRising Edge CLK to Rising Edge FBIN (133MHz)
Output Skew between 3.3V Outputs
Output Skew between 2.5V Outputs
Output Skew between 2.5V and 3.3V Outputs
Cycle-to-Cycle Output Jitter (Peak-to-Peak) at 133MHz
Duty Cycle
Output Rise Time for 3.3V Outputs (20% to 80%)
Output Fall Time for 3.3V Outputs (20% to 80%)
Output Rise Time for 2.5V Outputs (20% to 80%)
Output Fall Time for 2.5V Outputs (20% to 80%)
t
R
t
F
t
R
t
F
SWITCHING CHARACTERISTICS OV ER OPERATING RANGE - 5V 2528A
(1)
Parameter
(2)
t
PHASE
error
Phase Error fromRising Edge CLK to Rising Edge FBIN (100MHz-166MHz)
t
PHASE
error - jitter
(3)
Phase Error mnus Jitter fromRising Edge CLK to Rising Edge FBIN (166MHz)
t
SK
1(0)
(4)
Output Skew between 3.3V Outputs
t
SK
2(0)
(4)
Output Skew between 2.5V Outputs
t
SK
3(0)
(4,5)
Output Skew between 2.5V and 3.3V Outputs
25MHz to 133MHz
133MHz to 166MHz
t
J
Cycle-to-Cycle Output Jitter (Peak-to-Peak) at 166MHz
Duty Cycle
t
R
Output Rise Time for 3.3V Outputs (20% to 80%)
t
F
Output Fall Time for 3.3V Outputs (20% to 80%)
t
R
Output Rise Time for 2.5V Outputs (20% to 80%)
t
F
Output Fall Time for 2.5V Outputs (20% to 80%)
Symbol
Min.
–
150
–
50
—
—
—
—
–
75
45
0.8
0.8
0.5
0.5
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
Max.
150
50
150
150
200
250
75
55
2.1
2.1
1.5
1.5
Unit
ps
ps
ps
ps
ps
ps
%
ns
ns
ns
ns
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