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參數(shù)資料
| 型號(hào)： | IDT5V2528APGI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 2.5V / 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER |
| 中文描述： | 5V SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | TSSOP-28 |
| 文件頁(yè)數(shù)： | 3/7頁(yè) |
| 文件大?。?/td> | 61K |
| 代理商： | IDT5V2528APGI |
3
INDUSTRIAL TEMPERATURE RANGE
IDT5V2528/A
2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER
PIN DESCRIPTION
Terminal
Name
CLK
(1)
FBIN
G_Ctrl
(2)
No.
6
7
28
Type
I
I
3-level
Description
Clock input
Feedback input
3-level input for 2.5V / 3.3V Output Select/ Output bank enable. When G_Ctrl is LOW, all outputs except FBOUT are disabled
to a logic-LOW state. When G_Ctrl is MID or HIGH, all outputs are enabled and switch at the same frequency as CLK (see
OUTPUT SELECTION table).
3-level input for 2.5V / 3.3V Output Select (see OUTPUT SELECTION table)
Feedback output
2.5V or 3.3V Clock outputs. 1, 2, 3, 5, or 7 of these outputs may be selected as 2.5V outputs (see OUTPUT SELECTION table).
T_Ctrl
(2)
FBOUT
TY
(7:0)
1
22
3-level
O
O
3, 10, 12, 13,
16, 17, 24, 26
19, 20
5
8
21
4, 11, 15, 25
2, 9, 14, 18
23, 27
Y
(1:0)
AV
DD(3)
AGND
V
DD
V
DDQ
GND
O
3.3V Clock Outputs
3.3V Analog power supply. AV
DD
provides the power reference for the analog circuitry.
Analog ground. AGND provides the ground reference for the analog circuitry.
3.3V Power supply
2.5V or 3.3V Power supply for TY outputs
Ground
Power
Ground
Power
Power
Ground
NOTES:
1. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time of 1ms
is required for the PLL to phase lock the feedback signal to the reference signal.
2. 3-level inputs will float to MID logic level if left unconnected.
3. AV
DD
can be used to bypass the PLL for test purposes. When AV
DD
is strapped to ground, PLL is bypassed and CLK is buffered directly to the outputs.
OUTPUT SELECTION
V
DDQ
G_Ctrl
M
T_Ctrl
L
TY
(7:0)
TY
0
(2.5V)
TY
1
- TY
7
(3.3V)
TY
1,
TY
2
(2.5V)
TY
0,
TY
3
- TY
7
(3.3V)
TY
0
- TY
2
(2.5V)
TY
3
- TY
7
(3.3V)
TY
0
- TY
4
(2.5V)
TY
5
- TY
7
(3.3V)
TY
1
- TY
7
(2.5V)
TY
0
(3.3V)
TY
o
- TY
7
(3.3V)
Configuration
Pin 4 (2.5V)
Pins 11, 15, 25 (3.3V)
Pin 25 (2.5V)
Pins 4, 11, 15 (3.3V)
Pins 4, 25 (2.5V)
Pins 11, 15 (3.3V)
Pins 4, 15, 25 (2.5V)
Pins 11, 15, 25 (2.5V)
Pin 4 (3.3V)
Pins 4, 11, 15, 25 (3.3V)
M
M
M
H
H
L
H
M
H
H
STATIC FUNCTION TABLE
(A
VDD
= 0V)
(1)
Inputs
G_Ctrl
T_Ctrl
CLK
L
X
L
L
X
H
see
H
OUTPUT SELECTION
L
table
running
Outputs
Y
(1:0)
L
L
H
L
running
TY
(7:0)
L
L
H
L
running
FBOUT
L
H
H
L
running
DY NAMIC FUNCTION TABLE
(A
VDD
= 3.3V)
Inputs
G_Ctrl
T_Ctrl
CLK
L
X
L
L
X
H
see OUTPUT
L
SELECTION table
H
Outputs
Y
(1:0)
L
L
L
H
TY
(7:0)
L
L
L
H
FBOUT
L
H
L
H
NOTE:
1. AV
DD
should be powered up along with V
DD
, before setting AV
DD
to ground, to put the
control pins in a valid state.
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| IDT5V2528PGGI | 功能描述:IC CLK DVR ZD BUFFER PLL 28TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
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