參數(shù)資料
型號(hào)： IDT5V19EE604NDGI
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 26/29頁(yè)
文件大?。?/td> 0K
描述： IC PLL CLK GEN 200MHZ 28VFQFPN
產(chǎn)品培訓(xùn)模塊： VersaClock™ III Programmable Clocks
特色產(chǎn)品： VersaClock III Timing Devices
標(biāo)準(zhǔn)包裝： 75
系列： VersaClock™ III
類型： 時(shí)鐘發(fā)生器，多路復(fù)用器
PLL： 帶旁路
輸入： LVCMOS，LVTTL，晶體
輸出： LVCMOS，LVTTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:6
差分 - 輸入:輸出： 無(wú)/無(wú)
頻率 - 最大： 200MHz
除法器/乘法器： 是/是
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 28-VFQFPN（4x4）
包裝： 管件
其它名稱： 800-1922
IDT5V19EE604
EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR
CLOCK SYNTHESIZER
IDT EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR
6
IDT5V19EE604
REV M 092412
Reference Clock Input Pins and
Selection
The IDT5V19EE604 supports up to two clock inputs. One of
the clock inputs (XIN/ REF) can be driven by either an
external crystal or a reference clock. The second clock input
(CLKIN) can only be driven from an external reference
clock. The CLKSEL pin selects the input clock from either
XTAL/REF or CLKIN.
Either clock input can be set as the primary clock. The
primary clock designation is to establish which is the main
reference clock to the PLLs. The non-primary clock is
designated as the secondary clock in case the primary clock
goes absent and a backup is needed. The PRIMSRC bit
(0xBE through 0xC3) determines which clock input will be
selected as primary clock. When PRIMSRC bit is "0",
XIN/REF is selected as the primary clock, and when "1",
CLKIN as the primary clock.
The two external reference clocks can be manually selected
using the CLKSEL pin. The SM bits (0xBE through 0xC3)
must be set to "0x" for manual switchover which is detailed
in SWITCHOVER MODES section.
Crystal Input (XIN/REF)
The crystal used should be a fundamental mode quartz
crystal; overtone crystals should not be used.
When the XIN/REF pin is driven by a crystal, it is important
to set the internal inverter oscillator drive strength and
tuning/load capacitor values correctly to achieve the best
clock performance. These values are programmable
through I2C interface to allow for maximum compatibility
with crystals from various manufacturers, processes,
performances, and qualities. The internal load capacitors
are true parallel-plate capacitors for ultra-linear
performance. Parallel-plate capacitors were chosen to
reduce the frequency shift that occurs when non-linear load
capacitance interacts with load, bias, supply, and
temperature changes. External non-linear crystal load
capacitors should not be used for applications that are
sensitive to absolute frequency requirements. The value of
the internal load capacitors are determined by XTAL[4:0]
bits. The load capacitance can be set with a resolution of
0.125 pF for a total crystal load ranging from 3.5 pF to 7.5
pF. Check with the crystal vendor's load capacitance
specification for the exact setting to tune the internal load
capacitor. The following equation governs how the total
internal load capacitance is set.
XTAL load cap = 3.5 pF + XTAL[4:0] * 0.125 pF (Eq. 1)
When using an external reference clock instead of a crystal
on the XTAL/REF pin, the input load capacitors may be
completely bypassed. This allows for the input frequency to
be up to 200 MHz. When using an external reference clock,
the XOUT pin must be left floating, XTAL must be
programmed to the default value of “00h”, and the crystal
drive strength bit, XDRV (0x06), must be set to the default
value of “11h”.
Switchover Modes
The IDT5V19EE604 features redundant clock inputs which
supports both Automatic and Manual switchover mode.
These two modes are determined by the configuration bits,
SM (0xBE through 0xC3). The primary clock source can be
programmed, via the PRIMSRC bit, to be either XIN/REF or
CLKIN. The other clock input will be considered as the
secondary source. Note that the switchover modes are
asynchronous. If the reference clocks are directly routed to
OUTx with no phase relationship, short pulses can be
generated during switchover. The automatic switchover
mode will work only when the primary clock source is
XIN/REF. Switchover modes are not supported for crystal
input configurations.
Manual Switchover Mode
When SM[1:0] is "0x", the redundant inputs are in manual
switchover mode. In this mode, CLKSEL pin is used to
switch between the primary and secondary clock sources.
As previously mentioned, the primary and secondary clock
source setting is determined by the PRIMSRC bit. During
the switchover, no glitches will occur at the output of the
device, although there may be frequency and phase drift,
depending on the exact phase and frequency relationship
between the primary and secondary clocks.
Automatic Switchover Mode
The redundant inputs are in automatic switchover mode.
Automatic switchover mode has revertive functionality. The
input clock selection will switch to the secondary clock
source when there are no transitions on the primary clock
source for two secondary clock cycles. If both reference
Parameter
Bits
Step (pF)
Min (pF)
Max (pF)
XTAL
8
0.125
0
4
相關(guān)PDF資料
PDF描述
MS3122E20-41PY CONN RCPT 41POS BOX MNT W/PINS
VI-27T-MX-B1 CONVERTER MOD DC/DC 6.5V 75W
X9250TS24IZ-2.7T1 IC XDCP QUAD 256TP 100K 24-SOIC
X9250TS24IZ-2.7T2 IC XDCP QUAD 256TP 100K 24-SOIC
X9241AUVZ IC XDCP QUAD 4X50K EE 20-TSSOP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT5V19EE604NDGI8 功能描述:IC PLL CLK GEN 200MHZ 28VFQFPN RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:VersaClock™ III 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT
IDT5V19EE901NLGI 功能描述:IC PLL CLK GEN 200MHZ 32VFQFN RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:VersaClock™ III 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無(wú)/無(wú) 頻率 - 最大:1GHz 除法器/乘法器:是/無(wú) 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR
IDT5V19EE901NLGI8 功能描述:IC PLL CLK GEN 200MHZ 32VFQFN RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:VersaClock™ III 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT
IDT5V19EE901PGGI 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GENERATOR
IDT5V19EE901PGGI8 制造商:Integrated Device Technology Inc 功能描述:IC CLK GEN VCXO PROGR 28TSSOP
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*