參數(shù)資料
型號： IDT5T915PAI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時鐘及定時
英文描述： 2.5V DIFFERENTIAL 1:5 CLOCK BUFFER TERABUFFER
中文描述： 5T SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
封裝： TSSOP-48
文件頁數(shù)： 5/19頁
文件大?。?/td> 127K
代理商： IDT5T915PAI
INDUSTRIAL TEMPERATURE RANGE
IDT5T915
2.5V DIFFERENTIAL 1:5 CLOCK BUFFER TERABUFFER
5
POWER SUPPLY CHARACTERISTICS FOR HSTL OUTPUTS
(1)
Symbol
Parameter
I
DDQ
Quiescent V
DD
Power Supply Current
V
DDQ
= Max., Reference Clock = LOW
(3)
Outputs enabled, All outputs unloaded
I
DDQQ
Quiescent V
DDQ
Power Supply Current
V
DDQ
= Max., Reference Clock = LOW
(3)
Outputs enabled, All outputs unloaded
I
DDD
Dynamc V
DD
Power Supply
V
DD
= Max., V
DDQ
= Max., C
L
= 0pF
Current per Output
I
DDDQ
Dynamc V
DDQ
Power Supply
V
DD
= Max., V
DDQ
= Max., C
L
= 0pF
Current per Output
I
TOT
Total Power V
DD
Supply Current
V
DDQ
= 1.5V, F
REFERENCE
CLOCK
= 100MHz, C
L
= 15pF
V
DDQ
= 1.5V, F
REFERENCE
CLOCK
= 250MHz, C
L
= 15pF
I
TOTQ
Total Power V
DDQ
Supply Current
V
DDQ
= 1.5V, F
REFERENCE
CLOCK
= 100MHz, C
L
= 15pF
V
DDQ
= 1.5V, F
REFERENCE
CLOCK
= 250MHz, C
L
= 15pF
Test Conditions
(2)
Typ.
20
Max
30
Unit
mA
0.1
0.3
mA
20
30
μ
A/MHz
30
50
μ
A/MHz
20
35
35
60
40
50
70
120
mA
mA
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termnation resistors are excluded fromthese measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
DC ELECTRICAL CHARACTERISTICS OV ER OPERATING RANGE FOR HSTL
(1)
Symbol
Parameter
Test Conditions
Input Characteristics
I
IH
Input HIGH Current
(9)
V
DD
= 2.6V
I
IL
Input LOW Current
(9)
V
DD
= 2.6V
V
IK
Clamp Diode Voltage
V
DD
= 2.4V, I
IN
= -18mA
V
IN
DC Input Voltage
V
DIF
DC Differential Voltage
(2,8)
V
CM
DC Common Mode Input Voltage
(3,8)
V
IH
DC Input HIGH
(4,5,8)
V
IL
DC Input LOW
(4,6,8)
V
REF
Single-Ended Reference Voltage
(4,8)
Output Characteristics
V
OH
Output HIGH Voltage
I
OH
= -8mA
I
OH
= -100
μ
A
V
OL
Output LOW Voltage
I
OL
= 8mA
I
OL
= 100
μ
A
Min.
Typ.
(7)
Max
Unit
V
I
= V
DDQ
/GND
V
I
= GND/V
DDQ
—
—
—
- 0.3
0.2
680
—
—
- 0.7
±5
±5
- 1.2
+3.6
—
900
—
μ
A
V
V
V
750
mV
mV
mV
mV
V
REF
+ 100
—
—
V
REF
- 100
—
750
V
DDQ
- 0.4
V
DDQ
- 0.1
—
—
—
—
0.4
0.1
V
V
V
V
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. V
DIF
specifies the mnimuminput differential voltage (V
TR
- V
CP
) required for switching where V
TR
is the "true" input level and V
CP
is the "complement" input level. Differential mode
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching
to a new state.
3. V
CM
specifies the maximumallowable range of (V
TR
+ V
CP
) /2. Differential mode only.
4. For single-ended operation, in differential mode,
A
/V
REF
is tied to the DC voltage V
REF
.
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
7. Typical values are at V
DD
= 2.5V, V
DDQ
= 1.5V, +25°C ambient.
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be
referenced.
9. For differential mode (RxS = LOW), A and
A
/V
REF
must be at the opposite rail.
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