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參數(shù)資料
| 型號： | ID82C52 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS Serial Controller Interface |
| 中文描述： | 1 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, CDIP28 |
| 封裝： | CERAMIC, DIP-28 |
| 文件頁數(shù)： | 3/19頁 |
| 文件大?。?/td> | 255K |
| 代理商： | ID82C52 |
5-3
DSR
18
I
Low
DATA SET READY: The logical state of the DSR line is reflected in the Modem Status Register.
Any change of state of DSR will cause INTR to be set if INTEN and MIEN are true. The state
of this signal does not affect any other circuitry within the 82C52.
DTR
19
O
Low
DATA TERMINAL READY: The DTR signal can be set (low) by writing a logic 1 to the appro-
priate bit in the Modem Control Register (MCR). This signal is cleared (high) by writing a logic
0 in the DTR bit in the MCR or whenever a reset (RST = high) is applied to the 82C52.
RTS
20
O
Low
REQUEST TO SEND: The RTS signal can be set (low) by writing a logic 1 to the appropriate
bit in the MCR. This signal is cleared (high) by writing a logic 0 to the RTS bit in the MCR or
whenever a reset (RST = high) is applied to the 82C52.
CO
21
O
CLOCK OUT: This output is user programmable to provide either a buffered IX output or a
buffered Baud Rate Generator (16X) clock output. The buffered IX (Crystal or external clock
source) output is provided when the Baud Rate Select Register (BRSR) bit 7 is set to a zero.
Writing a logic one to BRSR bit 7 causes the CO output to provide a buffered version of the
internal Baud Rate Generator clock which operates at sixteen times the programmed baud
rate. On reset D7 (CO select) is reset to 0.
TBRE
22
O
High
TRANSMITTER BUFFER REGISTER EMPTY: The TBRE output is set (high) whenever the
Transmitter Buffer Register (TBR) has transferred its data to the Transmit Register. Application
of a reset (RST) to the 82C52 will also set the TBRE output. TBRE is cleared (low) whenever
data is written to the TBR.
RST
23
I
High
RESET: The RST input forces the 82C52 into an “Idle” mode in which all serial data activities
are suspended. The Modem Control Register (MCR) along with its associated outputs are
cleared. The UART Status Register (USR) is cleared except for the TBRE and TC bits, which
are set. The 82C52 remains in an “Idle” state until programmed to resume serial data activities.
The RST input is a Schmitt triggered input.
INTR
24
O
High
INTERRUPT REQUEST: The INTR output is enabled by the INTEN bit in the Modem Control
Register (MCR). The MIEN bit selectively enables modem status changes to provide an input
to the INTR logic. Figure 9 in Design Information shows the overall relationship of these inter-
rupt control signals.
SDI
25
I
High
SERIAL DATA INPUT: Serial data input to the 82C52 receiver circuits. A Mark (1) is high, and
a Space (0) is low. Data inputs on SDI are disabled when operating in the loop mode or when
RST is true.
DR
26
O
High
DATA READY: A true level indicates that a character has been received, transferred to the
RBR, and is ready for transfer to the CPU. DR is reset on a data READ of the Receiver Buffer
Register (RBR) or when RST is true.
V
CC
27
High
V
CC
: +5V positive power supply pin. A 0.1
μ
F decoupling capacitor from V
CC
(Pin 27) to GND
(Pin 16) is recommended.
CS0
28
I
Low
CHIP SELECT: The chip select input acts as an enable signal for the RD and WR input
signals.
Pin Description
(Continued)
SYMBOL
PIN
NO.
TYPE
ACTIVE
LEVEL
DESCRIPTION
82C52
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