參數(shù)資料
型號(hào): ID82C52
廠商: INTERSIL CORP
元件分類: 微控制器/微處理器
英文描述: CMOS Serial Controller Interface
中文描述: 1 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, CDIP28
封裝: CERAMIC, DIP-28
文件頁(yè)數(shù): 16/19頁(yè)
文件大?。?/td> 255K
代理商: ID82C52
5-16
FIGURE 19. RECEIVE TIMING
FIGURE 20. OTHER TIMING
NOTES:
1. DR bit D7 in USR is updated each time DR changes state. TDRH always from trailing edge of 11th CO(BRG) in last Stop bit.
2. INTR on receive flags OE, FE, PE, and RBRK: INTEN enabled; Respective USR bits updated at this time regardless of interrupt config-
uration.
- INT on OE, FE, PE, RBRK occurs from the trailing edge of the 11th CO(BRG) in the last Stop bit. To avoid OE, RD(RBR) must go low
by the trailing edge of the 8th CO(BRG) in the last Stop bit.
3. INTR on MS: INTEN and MIEN enabled; USR bit D4(MS) is updated at this time regardless of INTEN/MIEN.
- INTR on MS occurs whenever CTS or DSR input changes state.
UART Timing Characterization
(Continued)
CO(BRG)
SDI
DR
INTR
11
12
13
14
15
16
1/I
2/I
3/I
(23)
TRLIL
(26)
TRLDL
USR
RBR
START BIT / IDLE
(25)
TDRH
(21)
TIHF
RD
LAST STOP BIT
NOTE 1
NOTE 2
INTR
DSR/CTS
RD
RTS/DTR
WR
(23)
TRLIL
(22)
TIHM
MSR
(27)
TWHO
MCR
NOTE 3
82C52
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