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參數(shù)資料
| 型號(hào)： | ID82C52 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS Serial Controller Interface |
| 中文描述： | 1 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, CDIP28 |
| 封裝： | CERAMIC, DIP-28 |
| 文件頁數(shù)： | 15/19頁 |
| 文件大小： | 255K |
| 代理商： | ID82C52 |
5-15
FIGURE 18. TRANSMIT TIMING
NOTES:
1. TBRE bit D6 in USR is updated each time TBRE changes state.
2. A.
With TR initially empty, TCLTH(TBRE) occurs from the 4th falling edge of CO(BRG) after WR goes high.
B. With TR initially full, TCLTH(TBRE) occurs from the trailing edge of the 15th CO(BRG) in the last Stop bit provided WR went high by
the trailing edge of the 12th CO(BRG) in the last Stop bit.
3. A.
With TR (Transmitter Register) initially empty, TDTX occurs from the 5th falling edge of CO(BRG) after WR goes high.
B. With TR initially full, TDTX occurs from the trailing edge of the 16th CO(BRG) in the last Stop bit provided WR went high by the trailing
edge of the 12th CO(BRG) in the last Stop bit.
4. TCTHX is time before end of last Stop bit by which CTS must be inactive (high) to prevent transmission of the character waiting in TBR.
5. With CTS high (disable transmit) and TBR full, TCLTH(TBRE) occurs from the 4th falling edge of CO(BRG) after CTS goes low.
6. With CTS high (disable transmit) and TBR full, TDTX occurs from the 5th falling edge of CO(BRG) after CTS goes low.
UART Timing Characterization
(Continued)
CO(BRG)
TBRE
SDO
INTR
(19)
TWLTL
(20)
TCLTH
(18)
TDTX
IDLE / START BIT
LAST STOP BIT / IDLE
(21)
TIHF
(23)
TRLIL
RD
WR
CO(BRG)
9/I
10/I
11/I
12/I
13/I
14/I
15/I
16/I
I/1
I/2
I/3
8/I
12
13
14
15
16
11
SDO
TBRE
CTS
1
2
START BIT
(18)
TDTX
(20)
TCLTH
IDLE
DISABLED
LAST STOP BIT
(24)
TCTHX
NOTE 1
NOTE 5
NOTE 6
NOTE 4
NOTE 2
NOTE 3
82C52
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| ID82C52/+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UART |
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| ID82C54/+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Timer Circuit |
| ID82C54-10 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Programmable Interval Timer |
| ID82C54-12 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Programmable Interval Timer |
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