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參數(shù)資料
| 型號： | ICSXXXXYFLFT |
| 英文描述： | 26/SKT/TB/2R/10AVE/90:10 |
| 中文描述： | 系統(tǒng)時(shí)鐘芯片的支持ATI RS400 P4TM的系統(tǒng) |
| 文件頁數(shù)： | 11/19頁 |
| 文件大小： | 206K |
| 代理商： | ICSXXXXYFLFT |
11
Integrated
Circuit
Systems, Inc.
ICS951411
0891E—03/07/05
Absolute Max
Symbol
VDD_A
VDD_In
Ts
Tambient
Tcase
Parameter
Min
Max
Units
V
V
°
C
°C
°C
3.3V Core Supply Voltage
3.3V Logic Input Supply Voltage
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
human body model
V
DD
+ 0.5V
V
DD
+ 0.5V
150
70
115
GND - 0.5
-65
0
ESD prot
2000
V
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70°C; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Notes
Input High Voltage
Input Low Voltage
Input High Current
V
IH
V
IL
I
IH
3.3 V +/-5%
3.3 V +/-5%
V
IN
= V
DD
2
V
DD
+ 0.3
0.8
5
V
V
uA
1
1
1
V
SS
- 0.3
-5
I
IL1
V
IN
= 0 V; Inputs with no pull-up
resistors
V
IN
= 0 V; Inputs with pull-up
resistors
-5
uA
1
I
IL2
-200
uA
1
Low Threshold Input-
High Voltage
Low Threshold Input-
Low Voltage
Operating Current
V
IH_FS
3.3 V +/-5%
0.7
V
DD
+ 0.3
V
1
V
IL_FS
3.3 V +/-5%
V
SS
- 0.3
0.35
V
1
I
DD3.3OP
all outputs driven
all diff pairs driven
all differential pairs tri-stated
V
DD
= 3.3 V
400
70
12
mA
mA
mA
MHz
nH
pF
pF
pF
1
1
1
3
1
1
1
1
Input Frequency
Pin Inductance
F
i
L
pin
C
IN
C
OUT
C
INX
14.31818
7
5
6
5
Logic Inputs
Output pin capacitance
X1 & X2 pins
From V
DD
Power-Up or de-
assertion of PD# to 1st clock
Triangular Modulation
CPU output enable after
PD# de-assertion
PD# fall time of
PD# rise time of
Clk Stabilization
T
STAB
1.8
ms
1,2
Modulation Frequency
30
33
kHz
1
Tdrive_PD#
300
us
1
Tfall_Pd#
Trise_Pd#
SMBus Voltage
Low-level Output Voltage
Current sinking at
V
OL
= 0.4 V
SCLK/SDATA
Clock/Data Rise Time
SCLK/SDATA
Clock/Data Fall Time
1
Guaranteed by design and characterization, not 100% tested in production.
2
See timing diagrams for timing requirements.
3
Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz to meet
5
5
ns
ns
V
V
1
2
1
1
V
DD
V
OL
2.7
5.5
0.4
@ I
PULLUP
I
PULLUP
4
mA
1
T
RI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
(Min VIH + 0.15) to
(Max VIL - 0.15)
1000
ns
1
T
FI2C
300
ns
1
ppm frequency accuracy on PLL outputs.
Input Low Current
Powerdown Current
I
DD3.3PD
Input Capacitance
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| ICSXXXXYGLFT | 制造商:ICS 制造商全稱:ICS 功能描述:System Clock Chip for ATI RS400 P4TM-based Systems |
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