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| 型號(hào)： | ICSSSTUA32S865AHLF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 鎖存器 |
| 英文描述： | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA160 |
| 封裝： | 9 X 13 MM, LEAD FREE, BGA-160 |
| 文件頁(yè)數(shù)： | 8/17頁(yè) |
| 文件大?。?/td> | 199K |
| 代理商： | ICSSSTUA32S865AHLF-T |
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16
ICSSSTUA32S865A
1053A—03/21/05
Error output load circuit and voltage measurement information (VDD =1.8 V± 0.1V)
All input pulses are supplied by generators having the following characteristics: PRR
10 MHz;
Zo =50 ; input slew rate = 1 V/ns ± 20%, unless otherwise specified.
(1) CL includes probe and jig capacitance.
Figure 16 — Load circuit, error output measurements
Figure 17 — Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to RESET
input
Figure 18 — Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect to clock
inputs
Figure 19 — Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to clock
inputs
CL = 10 pF
SEE NOTE (1)
VDD
OUT
DUT
TEST POINT
RL = 1 k
002aaa500
VCC/2
tPLH
VCC
0 V
0.15 V
VOH
0 V
Output
Waveform 2
LVCMOS
RESET
Input
002aaa501
VICR
tHL
VCC/2
VCC
VOL
Timing
Inputs
Output
Waveform 1
VI(PP)
VICR
002aaa502
VICR
tLH
VOH
0 V
Timing
Inputs
Output
Waveform 2
VI(PP)
VICR
0.15 V
002aaa503
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