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參數(shù)資料
| 型號(hào)： | ICSSSTUA32S865AHLF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 鎖存器 |
| 英文描述： | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA160 |
| 封裝： | 9 X 13 MM, LEAD FREE, BGA-160 |
| 文件頁數(shù)： | 7/17頁 |
| 文件大小： | 199K |
| 代理商： | ICSSSTUA32S865AHLF-T |
15
ICSSSTUA32S865A
1053A—03/21/05
Output slew rate measurement information (VDD =1.8 V±0.1V)
All input pulses are supplied by generators having the following characteristics: PRR
10 MHz;
Zo =50 ; input slew rate = 1 V/ns ± 20%, unless otherwise specified.
(1) CL includes probe and jig capacitance.
Figure 12 — Load circuit, HIGH-to-LOW slew measurement
Figure 13 — Voltage waveforms, HIGH-to-LOW slew rate measurement
(1) CL includes probe and jig capacitance.
Figure 14 — Load circuit, LOW-to-HIGH slew measurement
Figure 15 — Voltage waveforms, LOW-to-HIGH slew rate measurement
CL = 10 pF
SEE NOTE (1)
VDD
OUT
DUT
TEST POINT
RL = 50
002aaa377
VOH
VOL
OUTPUT
80%
20%
dv_f
dt_f
002aaa378
CL = 10 pF
SEE NOTE (1)
OUT
DUT
TEST POINT
RL = 50
002aaa379
VOH
VOL
80%
20%
dv_r
dt_r
OUTPUT
002aaa380
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