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參數(shù)資料
| 型號： | ICSSSTUA32S865AHLF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 鎖存器 |
| 英文描述： | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA160 |
| 封裝： | 9 X 13 MM, LEAD FREE, BGA-160 |
| 文件頁數(shù)： | 6/17頁 |
| 文件大?。?/td> | 199K |
| 代理商： | ICSSSTUA32S865AHLF-T |
14
ICSSSTUA32S865A
1053A—03/21/05
Notes: 1. CL includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: PRR
≤ 10MHz, ZO =
50
, input slew rate = 1 V/ns ±20% (unless otherwise specified).
Figure 7 — Output Slew-Rate M easurement I nfor mation (V DD = 1.8 V ± 0.1 V)
CL = 10 pF
(see Note 1)
LOAD CIRCUIT – HIGH-TO-LOW SLEW-RATE MEASUREMENT
Test Point
DUT
Out
dt _f
VOL
VOH
VOLTAGE WAVEFORMS – HIGH-TO-LOW SLEW-RATE MEASUREMENT
80%
Output
20%
dv _f
RL = 50
CL = 10 pF
(see Note 1)
LOAD CIRCUIT – LOW-TO-HIGH SLEW-RATE MEASUREMENT
Test Point
DUT
Out
dt _r
VOL
VOH
VOLTAGE WAVEFORMS – LOW-TO-HIGH SLEW-RATE MEASUREMENT
80%
Output
20%
dv _r
RL = 50
VDD
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