參數(shù)資料
型號: ICS954204
英文描述: 16-Bit Registered Transceivers With 3-State Outputs 56-SSOP -40 to 85
中文描述: 可編程定時控制HubTM移動P4TM系統(tǒng)
文件頁數(shù): 3/16頁
文件大?。?/td> 199K
代理商: ICS954204
3
Integrated
Circuit
Systems, Inc.
ICS954204
0933D—03/16/05
Pin Description (Continued)
PIN # PIN NAME
Type
Pin Description
29
30
31
GND
SRCCLKC5
SRCCLKT5
PWR
OUT
OUT
Ground pin.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Output enable for PCI Express (SRC) outputs. SMBus selects which outputs
are controlled.
0 = enabled, 1 = tri-stated
Output enable for PCI Express (SRC) outputs. SMBus selects which outputs
are controlled.
0 = enabled, 1 = tri-stated
Supply for SRC clocks, 3.3V nominal
Complementary clock of CPU_ITP/SRC differential pair CPU_ITP/SRC
output. These are current mode outputs. External resistors are required for
voltage bias. Selected by ITP_EN input.
True clock of CPU_ITP/SRC differential pair CPU_ITP/SRC output. These
are current mode outputs. External resistors are required for voltage bias.
Selected by ITP_EN input.
3.3V power for the PLL core.
Ground pin for the PLL core.
32
CLKREQB#*
IN
33
CLKREQA#*
IN
34
VDDSRC
PWR
35
CPUCLKC2_ITP/SRCCLKC7
OUT
36
CPUCLKT2_ITP/SRCCLKT7
OUT
37
38
VDDA
GNDA
PWR
PWR
39
IREF
IN
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard value.
40
CPUCLKC1
OUT
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
41
CPUCLKT1
OUT
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
42
VDDCPU
PWR
43
CPUCLKC0
OUT
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
44
CPUCLKT0
OUT
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Ground pin.
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Ref, XTAL power supply, nominal 3.3V
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz.
Ground pin.
Reference Clock output
45
46
47
48
49
50
51
52
GND
SCLK
SDATA
VDDREF
X2
X1
GND
REFOUT
PWR
IN
I/O
PWR
OUT
IN
PWR
OUT
53
FSLC/TEST_SEL
IN
3.3V tolerant input for CPU frequency selection. Low voltage threshold
inputs, see input electrical characteristics for Vil_FS and Vih_FS values.
TEST_Sel: 3-level latched input to enable test mode.
Refer to Test Clarification Table
54
CPU_STOP#
IN
Stops all CPUCLK, except those set to be free running clocks
55
PCI/SRC_STOP#
IN
Stops all PCICLKs and SRCCLKs besides the free-running clocks at logic 0
level, when input low
PCI clock output.
56
*Pins 32 and 33 have pull-ups.
PCICLK2
OUT
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相關代理商/技術參數(shù)
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