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參數(shù)資料
| 型號： | ICS954101 |
| 英文描述： | 16-Bit Registered Transceivers With 3-State Outputs 56-TSSOP -40 to 85 |
| 中文描述： | 可編程定時控制中心系統(tǒng)的臺式機(jī)P4 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 132K |
| 代理商： | ICS954101 |
2
Integrated
Circuit
Systems, Inc.
ICS954101
0815D—06/21/04
Pin Description
Pin #
1
2
3
4
5
6
7
PIN NAME
PIN TYPE
PWR
PWR
OUT
OUT
OUT
PWR
PWR
DESCRIPTION
VDDPCI
GND
PCICLK3
PCICLK4
PCICLK5
GND
VDDPCI
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
Ground pin.
Power supply for PCI clocks, nominal 3.3V
Free running PCI clock not affected by PCI_STOP#.
ITP_EN: latched input to select pin functionality
1 = CPU_ITP pair
0 = SRC pair
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Power pin for the 48MHz output.3.3V
48.00MHz USB clock
Ground pin.
True clock of differential pair for 96.00MHz DOT clock.
Complement clock of differential pair for 96.00MHz DOT clock.
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time
input to select between Hi-Z and REF/N divider mode while in test mode.
Refer to Test Clarification Table.
Vtt_PwrGd# is an active low input used to determine when latched inputs
are ready to be sampled. PD is an asynchronous active high input pin
used to put the device into a low power state. The internal clocks, PLLs
and the crystal oscillator are stopped.
3.3V tolerant low threshold input for CPU frequency selection. This pin
requires CK410 FSA. Refer to input electrical characteristics for Vil_FS
and Vih_FS threshold values.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
Supply for SRC clocks, 3.3V nominal
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
True clock of differential SRC/SATA pair.
Complement clock of differential SRC/SATA pair.
Supply for SRC clocks, 3.3V nominal
8
ITP_EN/PCICLK_F0
I/O
9
PCICLK_F1
PCICLK_F2
VDD48
USB_48MHz
GND
DOTT_96MHz
DOTC_96MHz
OUT
OUT
PWR
OUT
PWR
OUT
OUT
10
11
12
13
14
15
16
FS_B/TEST_MODE
IN
17
Vtt_PwrGd#/PD
IN
18
FS_A_410
IN
19
20
21
22
23
24
25
26
27
28
SRCCLKT1
SRCCLKC1
VDDSRC
SRCCLKT2
SRCCLKC2
SRCCLKT3
SRCCLKC3
SRCCLKT4_SATA
SRCCLKC4_SATA
VDDSRC
OUT
OUT
PWR
OUT
OUT
OUT
OUT
OUT
OUT
PWR
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參數(shù)描述 |
|---|---|
| ICS954101DFLF | 功能描述:IC TIMING CTRL HUB P4 56-SSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 專用 系列:TCH™, PCI Express® (PCIe) 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| ICS954101DFLFT | 功能描述:IC CTRL HUB PROGR TIMING 56-SSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 專用 系列:TCH™, PCI Express® (PCIe) 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| ICS954101DGLF | 功能描述:IC TIMING CTRL HUB P4 56-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 專用 系列:TCH™, PCI Express® (PCIe) 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| ICS954101DGLFT | 功能描述:IC TIMING CTRL HUB P4 56-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 專用 系列:TCH™, PCI Express® (PCIe) 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| ICS954101YFLFT | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub for Desktop P4 Systems |
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