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參數(shù)資料
| 型號： | ICS952621YFLF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | LEAD FREE, MO-118, SSOP-48 |
| 文件頁數(shù)： | 17/17頁 |
| 文件大?。?/td> | 155K |
| 代理商： | ICS952621YFLF-T |
9
Integrated
Circuit
Systems, Inc.
ICS952621
0756C—04/19/05
I
2C Table: Read-Back Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
RESERVED
-
X
Bit 6
-X
Bit 5
-X
Bit 4
RX
Bit 3
RX
Bit 2
RX
Bit 1
FSB
Freq Select 1 Read
Back
RX
Bit 0
FSA
Freq Select 0 Read
Back
RX
I
2C Table: Spreading and Device Behavior Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
SRC/SRC#
SRC Free-Running
Control
RW
FREE-
RUN
STOPPAB
LE
0
Bit 6
SRC
Output Control
RW
Disable
Enable
1
Bit 5
RX
Bit 4
RX
Bit 3
RX
Bit 2
RX
Bit 1
CPUT1/CPUC1
Output Control
RW
Disable
Enable
1
Bit 0
CPUT0/CPUC0
Output Enable
RW
Disable
Enable
1
I
2C Table: Output Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
SRC_PD#
Drive Mode
0: Driven in PD#
RW
Driven
Hi-Z
0
Bit 6
SRC_Stop#
Drive Mode
0: Driven in
PCI_Stop#
RW
Driven
Hi-Z
0
Bit 5
RESERVED
-
X
Bit 4
CPUT1_PD# Drive Mode
RW
Driven
Hi-Z
0
Bit 3
CPUT0_PD# Drive Mode
RW
Driven
Hi-Z
0
Bit 2
RESERVED
-
X
Bit 1
RESERVED
-
X
Bit 0
RESERVED
-
X
I
2C Table: Output Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
PCI_Stop#
PCI_Stop# Control
0:all stoppable PCI
are stopped
RW
Enable
Disable
1
Bit 6
RESERVED
-
X
Bit 5
PCICLK5
Output Control
RW
Disable
Enable
1
Bit 4
PCICLK4
Output Control
RW
Disable
Enable
1
Bit 3
PCICLK3
Output Control
RW
Disable
Enable
1
Bit 2
PCICLK2
Output Control
RW
Disable
Enable
1
Bit 1
PCICLK1
Output Control
RW
Disable
Enable
1
Bit 0
PCICLK0
Output Control
RW
Disable
Enable
1
RESERVED
-
RESERVED
READBACK of
CPU(2:0) Frequency
Byte 2
RESERVED
Byte 1
RESERVED
-
RESERVED
-
Byte 0
-
Byte 3
RESERVED
0:driven in PD#
1: Tri-stated
RESERVED
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