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參數(shù)資料
| 型號： | ICS952607YFLF-T |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TV01; Number of Contacts:6; Connector Shell Size:9; Connecting Termination:Crimp; Circular Shell Style:Straight Receptacle; Body Style:Straight |
| 中文描述： | 可編程定時控制中心，為下一代P4處理器 |
| 文件頁數(shù)： | 9/21頁 |
| 文件大?。?/td> | 214K |
| 代理商： | ICS952607YFLF-T |
9
Integrated
Circuit
Systems, Inc.
ICS952607
Advance Information
0734—07/16/04
I
2
C Table: Output Control Register
Control
Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ASEL1
Reserved
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
3V66/PCI Freq Select
Reserved
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
RW
RW
RW
RW
RW
RW
RW
RW
0
0
1
1
1
1
1
1
Disable
Enable
See Table 5: Async AGP/PCI Freq Table
-
Disable
-
Disable
Disable
Enable
Enable
Disable
Disable
Enable
Enable
Enable
PWD
-
-
Byte 3
Pin #
Name
Type
0
1
20
19
16
15
14
13
Table 3: Linear M/N AGP/PCI Programmable Frequency Example
C
B
A
7
6
D
C
B
A
D
31
2D
29
1D
19
36
32
2E
2A
37
65.15
65.24
65.34
65.79
66.01
66.14
66.30
66.47
66.68
67.21
32.58
32.62
32.67
32.89
33.01
33.07
33.15
33.24
33.34
33.61
C
7
B
A
C
B
A
C
9
6
33
1E
2F
2B
34
30
2C
35
28
1B
67.44
67.57
67.70
68.01
68.58
68.93
69.34
69.73
69.83
70.01
33.72
33.78
33.85
34.01
34.29
34.47
34.67
34.86
34.91
35.01
Hex B5b3:0 Hex B6b6:0
AGP Freq
PCI Freq
Hex B5b3:0 Hex B6b6:0
AGP Freq
PCI Freq
I
2
C Table: Output Control Register
Control
Function
Bit 7
48MHz_0
2x output drive
0=2x drive
RW
0
Bit 6
SRCFS
SRC Frequency
Select
Reserved
Output Control
Output Control
Output Control
Output Control
Output Control
-
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
3V66_1
3V66_0
PCICLK_F2
PCICLK_F1
PCICLK_F0
RW
RW
RW
RW
RW
RW
0
1
1
1
1
1
I
2
C Table: Reserved Register
Control
Function
Bit 7
3V66_3/VCH
Select
Mode Sel1
Mode Sel0
3V66_3/VCH
M PLL2 Div3
M PLL2 Div2
M PLL2 Div1
M PLL2 Div0
Output Select
RW
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RW
RW
RW
RW
RW
RW
RW
0
0
1
X
X
X
X
Output Control
3V66
VCH
See Table 4: Mode Selection Table
Disable
Enable
Disable
Disable
Enable
Enable
Disable
Disable
Enable
Enable
100MHz
200MHz
Disable
Enable
-
-
The decimal representation of M PLL2 Div
(3:0) + 2 is equal to REF divider value for
PLL2
0
1
0
1
-
-
-
-
PWD
8
Byte 5
Pin #
Name
Type
PWD
2x drive
normal
Name
Type
Byte 4
Pin #
PLL Mode Selection
Bits
M Divider
Programming bits for
Async mode 2&3
26
-
-
-
30
31
10
9
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