參數(shù)資料
型號: ICS951403YGLF-T
元件分類: 時鐘產(chǎn)生/分配
英文描述: 166.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝: 0.240 INCH, 0.020 INCH PITCH, LEAD FREE, MO-153, TSSOP-48
文件頁數(shù): 7/18頁
文件大小: 639K
代理商: ICS951403YGLF-T
15
ICS951403
0486B—02/23/04
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS951403. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS951403 internally. PCICLK clocks are stopped in a low state and started with
a full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one
PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS951403 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS951403.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK
(Free-runningl)
CPU_STOP#
PWR_DWN#
PCICLK
(External)
PCI_STOP#
相關(guān)PDF資料
PDF描述
ICS951403YF-T 166.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS951403YFLF-T 166.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS951411YGLFT 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
ICS951412YGLFT 220 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
ICS951412YGT 220 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
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