參數(shù)資料
型號: ICS951403YGLF-T
元件分類: 時鐘產(chǎn)生/分配
英文描述: 166.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝: 0.240 INCH, 0.020 INCH PITCH, LEAD FREE, MO-153, TSSOP-48
文件頁數(shù): 6/18頁
文件大小: 639K
代理商: ICS951403YGLF-T
14
ICS951403
0486B—02/23/04
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power
operation. CPU_STOP# is synchronized by the ICS951403. All other clocks will continue to run while the CPUCLKs
clocks are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees
the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than
4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is
synchronized to the CPUCLKs inside the ICS951403.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
PCICLK
CPUCLKT
CPUCLKC
PD# (High)
CPU_STOP#
INTERNAL
CPUCLK
相關(guān)PDF資料
PDF描述
ICS951403YF-T 166.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS951403YFLF-T 166.67 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
ICS951411YGLFT 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
ICS951412YGLFT 220 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
ICS951412YGT 220 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
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