參數(shù)資料
型號(hào): ICS950902YGLF-T
英文描述: Programmable Timing Control Hub⑩ for P4⑩
中文描述: 可編程定時(shí)控制中心,為小四至⑩⑩
文件頁數(shù): 4/20頁
文件大?。?/td> 184K
代理商: ICS950902YGLF-T
4
Integrated
Circuit
Systems, Inc.
ICS950902
0475G—03/23/04
Pin Description Continued
PIN
PIN
#
NAME
29
DDRC5/SDRAM11
30
DDRT5/SDRAM10
31
DDRC4/SDRAM9
32
DDRT4/SDRAM8
33
GND
34
VDD3.3_2.5
35
DDRC3/SDRAM7
36
DDRT3/SDRAM6
37
DDRC2/SDRAM5
38
DDRT2/SDRAM4
39
GND
40
VDD3.3_2.5
41
DDRC1/SDRAM3
42
DDRT1/SDRAM2
43
DDRC0/SDRAM1
44
DDRT0/SDRAM0
45
BUF_IN
46
FBOUT
47
GND
48
CPUT_CS
49
CPUC_CS
50
VDDCPU2.5
51
VDDCPU3.3
PIN
TYPE
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
IN
OUT
PWR
OUT
OUT
PWR
PWR
"Complementary" Clock of differential memory output / 3.3V SDRAM clock output
"True" Clock of differential memory output / 3.3V SDRAM clock output
"Complementary" Clock of differential memory output / 3.3V SDRAM clock output
"True" Clock of differential memory output / 3.3V SDRAM clock output
Ground pin.
2.5V or 3.3V nominal power supply voltage.
"Complementary" Clock of differential memory output / 3.3V SDRAM clock output
"True" Clock of differential memory output / 3.3V SDRAM clock output
"Complementary" Clock of differential memory output / 3.3V SDRAM clock output
"True" Clock of differential memory output / 3.3V SDRAM clock output
Ground pin.
2.5V or 3.3V nominal power supply voltage.
"Complementary" Clock of differential memory output / 3.3V SDRAM clock output
"True" Clock of differential memory output / 3.3V SDRAM clock output
"Complementary" Clock of differential memory output / 3.3V SDRAM clock output
"True" Clock of differential memory output / 3.3V SDRAM clock output
Input Buffers for memory outputs.
Memory feed back output.
Ground pin.
"True" clocks of differential pair 2.5V push-pull CPU outputs.
Complementary" clocks of differential pair 2.5V push-pull CPU outputs.
Power pin for the CPUCLKs. 2.5V
Power pin for the CPUCLKs. 3.3V
"Complementary" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias / "Complementary" clocks of differential pair
CPU outputs. These open drain outputs need an external 1.5V pull-up / 2.5V CPU clock
output.
52
CPUCLKC/CPUCLKODC
OUT
53
CPUCLKT/CPUCLKODT
OUT
"True" clocks of differential pair CPU outputs. These are current mode outputs. External
resistors are required for voltage bias / "True" clocks of differential pair CPU outputs. These
open drain outputs need an external 1.5V pull-up / 2.5V CPU clock output.
54
55
GND
VDDREF
PWR
PWR
Ground pin.
Ref, XTAL power supply, nominal 3.3V
56
Vtt_PWRGD#**/REF1
IN
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are
valid and are ready to be sampled. This is an active low input. / 14.318 MHz reference clock.
DESCRIPTION
Mode Pin - Power Management Input Control
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相關(guān)PDF資料
PDF描述
ICS950902 Programmable Timing Control Hub⑩ for P4⑩
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參數(shù)描述
ICS950905 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub⑩ for P4⑩
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ICS950908BFLFT 功能描述:IC TIMING CTRL HUB P4 56-SSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:TCH™ 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP (0.240",6.10mm 寬) 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件
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