參數(shù)資料
型號: ICS950910
英文描述: Programmable Timing Control Hub for P4
中文描述: 可編程定時控制中心,為小
文件頁數(shù): 1/20頁
文件大小: 183K
代理商: ICS950910
Integrated
Circuit
Systems, Inc.
ICS950910
0735A—03/18/04
Pin Configuration
Recommended Application:
VIA P4X/P4M/KT/KN266/333 style chipsets.
Output Features:
1 - Pair of differential CPU clocks @ 3.3V (CK408)/
1 - Pair of differential open drain CPU clocks (K7)
1 - Pair of differential push pull CPU_CS clocks @ 2.5V
3 - AGP @ 3.3V
7 - PCI @ 3.3V
1 - 48MHz @ 3.3V fixed
1 - 24_48MHz @ 3.3V
2 - REF @ 3.3V, 14.318MHz
Key Specifications:
CPU_CS - CPUT/C: <±250ps
CPU_CS - AGP: <±250ps
CPU - DDR: <±250ps
PCI - PCI: <500ps
CPU - PCI: Min = 1.0ns, Typ = 2.0ns, Max = 4.0ns
Programmable Timing Control Hub for P4
Frequency Table
0
L
E
S
I
L
U
M
t
Z
g
T
r
d
o
T
c
a
B
m
,
R
e
c
=
R
*
n
e
R
f
3
V
D
D
)
t
t
p
O
e
C
Z
@
h
o
V
0
s
m
h
o
0
5
,
%
m
1
1
2
2
0
=
=
r
R
f
A
0
F
E
R
I
*
4
=
h
o
0
5
@
V
0
1
s
m
h
o
0
5
,
%
m
1
5
7
4
3
=
=
r
R
f
A
2
F
E
R
I
*
6
=
h
o
0
5
@
V
7
Bit7
Bit6
Bit5
Bit4
CPU
AGP
PCI
MHz
35.00
Spread %
Bit2
FS3
FS2
FS1
FS0
MHz
MHz
1
0
0
0
0
105.00
70.00
0.3 % Center Spread
1
0
0
0
1
140.00
70.00
35.00
0.3 % Center Spread
1
0
0
1
0
210.00
70.00
35.00
0.3 % Center Spread
1
0
0
1
1
174.99
70.00
35.00
0.3 % Center Spread
1
0
1
0
0
80.00
53.34
26.66
0.3 % Center Spread
1
0
1
0
1
106.66
53.34
26.66
0.3 % Center Spread
1
0
1
1
0
160.00
53.34
26.66
0.3 % Center Spread
1
0
1
1
1
133.33
53.34
26.66
0.3 % Center Spread
1
1
1
0
0
100.00
66.67
33.33
0.3 % Center Spread
1
1
1
0
1
133.33
66.67
33.33
0.3 % Center Spread
1
1
1
1
0
200.00
66.67
33.33
0.3 % Center Spread
1
1
1
1
1
166.66
66.67
33.33
0.3 % Center Spread
1
1
0
0
0
100.00
66.67
33.33
0 - 0.6% Down Spread
1
1
0
0
1
133.33
66.67
33.33
0 - 0.6% Down Spread
1
1
0
1
0
200.00
66.67
33.33
0 - 0.6% Down Spread
1
1
0
1
1
166.66
66.67
33.33
0 - 0.6% Down Spread
*FS0/REF0 1
GND 2
56 Vtt_PWRGD#**/REF1
55 VDDREF
54 GND
53 CPUCLKT/CPUCLKODT
52 CPUCLKC/CPUCLKODC
51 VDDCPU3.3
50 VDDCPU2.5
49 CPUC_CS
48 CPUT_CS
47 GND
46 FBOUT
45 BUF_IN
44 DDRT0
43 DDRC0
42 DDRT1
41 DDRC1
40 VDD2.5
39 GND
38 DDRT2
37 DDRC2
36 DDRT3
35 DDRC3
34 VDD2.5
33 GND
32 DDRT4
31 DDRC4
30 DDRT5
29 DDRC5
X1 3
X2 4
VDDAGP 5
*MODE/AGPCLK0 6
*SEL_408/K7/AGPCLK1 7
*(PCI_STOP#)AGPCLK2 8
GNDAGP 9
**FS1/PCICLK_F 10
***PCICLK1 11
*MULTSEL/PCICLK2 12
GNDPCI 13
PCICLK3 14
PCICLK4 15
VDDPCI 16
PCICLK5 17
*(CLK_STOP#)PCICLK6 18
GND48 19
*FS3/48MHz 20
*FS2/24_48MHz 21
AVDD48 22
VDD 23
GND 24
IREF 25
*(PD#)RESET# 26
SCLK 27
SDATA 28
56-SSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
*** A 120k pull-down resistor to GND is needed on this pin.
I
Features/Benefits:
Programmable output frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI control.
DDR output buffer supports up to 200MHz.
Watchdog timer technology to reset system
if system malfunctions.
Programmable watch dog safe frequency.
Support I
2
C Index read/write and block read/write
operations.
Uses external 14.318MHz crystal.
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