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參數(shù)資料
| 型號： | ICS950910 |
| 英文描述： | Programmable Timing Control Hub for P4 |
| 中文描述： | 可編程定時控制中心，為小 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大小： | 183K |
| 代理商： | ICS950910 |
4
Integrated
Circuit
Systems, Inc.
ICS950910
0735A—03/18/04
Pin Description (Continued)
PIN
#
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
PIN
NAME
DDRC5
DDRT5
DDRC4
DDRT4
GND
VDD2.5
DDRC3
DDRT3
DDRC2
DDRT2
GND
VDD2.5
DDRC1
DDRT1
DDRC0
DDRT0
BUF_IN
FBOUT
GND
CPUT_CS
CPUC_CS
VDDCPU2.5
VDDCPU3.3
PIN
TYPE
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
IN
OUT
PWR
OUT
OUT
PWR
PWR
"Complimentary" Clock of differential pair output.
"True" Clock of differential pair output.
"Complimentary" Clock of differential pair output.
"True" Clock of differential pair output.
Ground pin.
Power supply, nominal 2.5V
"Complimentary" Clock of differential pair output.
"True" Clock of differential pair output.
"Complimentary" Clock of differential pair output.
"True" Clock of differential pair output.
Ground pin.
Power supply, nominal 2.5V
"Complimentary" Clock of differential pair output.
"True" Clock of differential pair output.
"Complimentary" Clock of differential pair output.
"True" Clock of differential pair output.
Input Buffers for memory outputs.
Memory feed back output.
Ground pin.
True clock of differential pair 2.5V push-pull CPU outputs.
Complimentary" clocks of differential pair 2.5V push-pull CPU outputs.
Power pin for the CPUCLKs. 2.5V
Power pin for the CPUCLKs. 3.3V
"Complementary" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias / "Complementary" clocks of
differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up /
2.5V CPU clock output.
"True" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias / "True" clocks of differential pair CPU
outputs. These open drain outputs need an external 1.5V pull-up / 2.5V CPU clock
output.
Ground pin.
Ref, XTAL power supply, nominal 3.3V
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs
are valid and are ready to be sampled. This is an active low input. / 14.318 MHz
reference clock.
52
CPUCLKC/CPUCLKODC
OUT
53
CPUCLKT/CPUCLKODT
OUT
54
55
GND
VDDREF
PWR
PWR
56
Vtt_PWRGD#**/REF1
IN
DESCRIPTION
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| ICS951402AF | 功能描述:IC TIMING CTRL HUB P4 48-SSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:TCH™ 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| ICS951402AFLF | 功能描述:IC TIMING CTRL HUB P4 48-SSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:TCH™ 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| ICS951402AFLFT | 功能描述:IC TIMING CTRL HUB P4 48-SSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:TCH™ 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
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