參數(shù)資料
型號: ICS950902YGLF-T
英文描述: Programmable Timing Control Hub⑩ for P4⑩
中文描述: 可編程定時(shí)控制中心,為小四至⑩⑩
文件頁數(shù): 3/20頁
文件大?。?/td> 184K
代理商: ICS950902YGLF-T
3
Integrated
Circuit
Systems, Inc.
ICS950902
0475G—03/23/04
Pin Description
Pin description continued on next page.
PIN
#
1
2
3
4
5
PIN
NAME
*FS0/REF0
GND
X1
X2
VDDAGP
PIN
TYPE
I/O
PWR
IN
OUT
PWR
Frequency select latch input pin / 14.318 MHz reference clock.
Ground pin.
Crystal input,nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Power supply for AGP clocks, nominal 3.3V
6
*MODE/AGPCLK0
*SEL_408/K7/AGPCLK1
I/O
Function select latch input pin, 1=Desktop Mode, 0=Mobile Mode / AGP clock output.
7
I/O
CPU output type select latch input pin 0= K7, 1= CK408 / AGP clock output.
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low. This input
is activated by the MODE selection pin / AGP clock output.
Ground pin for the AGP outputs
Frequency select latch input pin / 3.3V PCI free running clock output.
8
*(PCI_STOP#)AGPCLK2
I/O
9
10
GNDAGP
**FS1/PCICLK_F
PWR
I/O
11
**SEL_SDR/DDR#/PCICLK1
I/O
Memory type select latch input pin 0= DDR, 1= PC133 SDRAM / 3.3V PCI clock output.
12
*MULTSEL/PCICLK2
I/O
3.3V LVTTL input for selection the current multiplier for CPU outputs / 3.3V PCI clock output.
13
14
15
16
17
GNDPCI
PCICLK3
PCICLK4
VDDPCI
PCICLK5
PWR
OUT
OUT
PWR
OUT
Ground pin for the PCI outputs
PCI clock output.
PCI clock output.
Power supply for PCI clocks, nominal 3.3V
PCI clock output.
Stops all CPU, DDR/SDRAM and FB_OUT clocks at logic 0 level, when input low. This input
is activated by the MODE selection pin / PCI clock output.
Ground pin for the 48MHz outputs
Frequency select latch input pin / Fixed 48MHz clock output. 3.3V
Frequency select latch input pin / Fixed 24 or 48MHz clock output. 3.3V.
Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V
Power supply, nominal 3.3V
Ground pin.
This pin establishes the reference current for the CPUCLK pairs. This pin requires a fixed
precision resistor tied to ground in order to establish the appropriate current.
18
*(CLK_STOP#)PCICLK6
I/O
19
20
21
22
23
24
GND48
*FS3/48MHz
*FS2/24_48MHz
AVDD48
VDD
GND
PWR
I/O
I/O
PWR
PWR
PWR
25
IREF
OUT
26
*(PD#)RESET#
I/O
Asynchronous active low input pin used to power down the device into a low power state.
This input is activated by the MODE selection pin / Real time system reset signal for
frequency gear ratio change or watchdog timer timeout. This signal is active low.
27
28
SCLK
SDATA
IN
I/O
Clock pin of I2C circuitry 5V tolerant
Data pin for I2C circuitry 5V tolerant
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
~ This output has 2X drive strength
DESCRIPTION
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PDF描述
ICS950902 Programmable Timing Control Hub⑩ for P4⑩
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參數(shù)描述
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