參數(shù)資料
型號(hào): ICS950812YGLFT
英文描述: Frequency Generator with 200MHz Differential CPU Clocks
中文描述: 頻率發(fā)生器200MHz的CPU的時(shí)鐘差分
文件頁數(shù): 2/29頁
文件大?。?/td> 225K
代理商: ICS950812YGLFT
2
ICS950812
0542G—08/21/03
Pin Configuration
PIN # PIN NAME
1
VDDREF
2
X1
3
X2
4
GND
5
PCICLK_F0
6
PCICLK_F1
7
PCICLK_F2
8
VDDPCI
9
GND
10
PCICLK0
11
**E_PCICLK1/PCICLK1
12
PCICLK2
13
**E_PCICLK3/PCICLK3
14
VDDPCI
15
GND
16
PCICLK4
17
PCICLK5
18
PCICLK6
19
VDD3V66
20
GND
21
66MHZ_OUT0/3V66_2
22
66MHZ_OUT1/3V66_3
23
66MHZ_OUT2/3V66_4
PIN TYPE
PWR
DESCRIPTION
Ref, XTAL power supply, nominal 3.3V
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
Early/Normal PCI clock output latched at power up.
PCI clock output.
Early/Normal PCI clock output latched at power up.
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
Power pin for the 3V66 clocks.
Ground pin.
3.3V 66.66MHz clock output selected via buffered or internal VCO.
3.3V 66.66MHz clock output selected via buffered or internal VCO.
3.3V 66.66MHz clock output selected via buffered or internal VCO.
3.3V 66.66MHz clock from internal VCO, 66MHZ input to 66MHz output and
PCI.
IN
OUT
PWR
OUT
OUT
OUT
PWR
PWR
OUT
I/O
OUT
I/O
PWR
PWR
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
24
66MHZ_IN/3V66_5
I/O
25
*PD#
IN
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal
are stopped. The latency of the power down will not be greater than 1.8ms.
26
27
VDDA
GND
PWR
PWR
3.3V power for the PLL core.
Ground pin.
This 3.3V LVTTL input is a level sensitive strobe used to determine when
latch inputs are valid and are ready to be sampled. This is an active low
input.
28
Vtt_PWRGD#
IN
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