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參數(shù)資料
| 型號(hào)： | ICS950201FLF-T |
| 英文描述： | Programmable Timing Control Hub⑩ for P4⑩ |
| 中文描述： | 可編程定時(shí)控制中心，為小四至⑩⑩ |
| 文件頁數(shù)： | 13/16頁 |
| 文件大小： | 206K |
| 代理商： | ICS950201FLF-T |
13
Integrated
Circuit
Systems, Inc.
ICS950201
0460G—08/31/04
The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low
in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising
edge.
PCI_STOP#
PCI_F[2:0] 33MHz
PCI[6:0] 33MHz
tsu
Assertion of PCI_STOP# Waveforms
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
CPU_STOP#
CPUT
CPUC
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I
2
C configuration to be stoppable via assertion
of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown. The final state
of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the output drive current values. The
CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
Assertion of CPU_STOP# Waveforms
CPU_STOP# Functionality
#
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS950201GLF-T | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub⑩ for P4⑩ |
| ICS950202 | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control HubTM for P4TM |
| ICS950202BF | 制造商:Ics 功能描述:PROGRAMMABLE TIMING CONTROL HUB FOR P4 |
| ICS950208 | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub for P4 |
| ICS950211 | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub for P4 |
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