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參數(shù)資料
| 型號： | ICS950201FLF-T |
| 英文描述： | Programmable Timing Control Hub⑩ for P4⑩ |
| 中文描述： | 可編程定時控制中心，為小四至⑩⑩ |
| 文件頁數(shù)： | 1/16頁 |
| 文件大小： | 206K |
| 代理商： | ICS950201FLF-T |
Integrated
Circuit
Systems, Inc.
ICS950201
0460G—08/31/04
Block Diagram
Pin Configuration
56-Pin SSOP & TSSOP
* These inputs have 150K internal pull-up resistor to VDD.
Frequency Table
Recommended Application:
CK-408 clock for Intel
845 chipset with P4 processor.
Output Features:
3 Differential CPU Clock Pairs @ 3.3V
7 PCI (3.3V) @ 33.3MHz
3 PCI_F (3.3V) @ 33.3MHz
1 USB (3.3V) @ 48MHz
1 DOT (3.3V) @ 48MHz
1 REF (3.3V) @ 14.318MHz
5 3V66 (3.3V) @ 66.6MHz
1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
Features:
Supports spread spectrum modulation,
down spread 0 to -0.5%.
Efficient power management scheme through PD#,
CPU_STOP# and PCI_STOP#.
Uses external 14.318MHz crystal
Stop clocks and functional control available through
I
2
C interface.
Key Specifications:
CPU Output Jitter <150ps
3V66 Output Jitter <250ps
CPU Output Skew <100ps, programmable over 800 ps
with groups CPU0,1 and CPU2.
Programmable Timing Control Hub for P4
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