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參數(shù)資料
| 型號： | ICS932S890CKLFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 7/21頁 |
| 文件大小： | 0K |
| 描述： | IC CLK CHIP EXPRESS 72MLF |
| 標準包裝： | 500 |
| 類型： | 時鐘/頻率合成器 |
| PLL： | 是 |
| 主要目的： | AMD CPU |
| 輸入： | 晶體 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:27 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 212.24MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 72-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 72-VFQFPN（10x10） |
| 包裝： | 帶卷 (TR) |
932S890C
RD890 SYSTEM CLOCK FOR AMD-BASED SERVERS
IDT
RD890 SYSTEM CLOCK FOR AMD-BASED SERVERS
15
932S890C
REV D 052011
SMBus Table: WD Timer Safe Frequency Control Register
Byte
10
Name
Control Function
Type
0
1
Default
Bit 7
SWD2
WD Soft Alarm Timer Bit 2
R W
1
Bit 6
SWD1
WD Soft Alarm Timer Bit 1
R W
1
Bit 5
SWD0
WD Soft Alarm Timer Bit 0
R W
1
Bit 4
WD SF4
R W
0
Bit 3
WD SF3
R W
0
Bit 2
WD SF2
R W
1
Bit 1
WD SF1
R W
0
Bit 0
WD SF0
R W
0
SMBus Table: CPU PLL Frequency Control Register
Byte
11
Name
Control Function
Type
0
1
Default
Bit 7
N Div2
N Divider Prog bit 2
R W
X
Bit 6
N Div1
N Divider Prog bit 1
R W
X
Bit 5
M Div5
R W
X
Bit 4
M Div4
R W
X
Bit 3
M Div3
R W
X
Bit 2
M Div2
R W
X
Bit 1
M Div1
R W
X
Bit 0
M Div0
R W
X
SMBus Table: CPU PLL Frequency Control Register
Byte
12
Name
Control Function
Type
0
1
Default
Bit 7
N Div10
R W
X
Bit 6
N Div9
RW
X
Bit 5
N Div8
RW
X
Bit 4
N Div7
RW
X
Bit 3
N Div6
RW
X
Bit 2
N Div5
RW
X
Bit 1
N Div4
RW
X
Bit 0
N Div3
RW
X
SMBus Table: CPU PLL Spread Spectrum Control Register
Byte
13
Name
Control Function
Type
0
1
Default
Bit 7
SSP7
R W
X
Bit 6
SSP6
R W
X
Bit 5
SSP5
R W
X
Bit 4
SSP4
R W
X
Bit 3
SSP3
R W
X
Bit 2
SSP2
R W
X
Bit 1
SSP1
R W
X
Bit 0
SSP0
R W
X
SMBus Table: CPU PLL Spread Spectrum Control Register
Byte
14
Name
Control Function
Type
0
1
Default
Bit 7
SSP15
R W
X
Bit 6
SSP14
R W
X
Bit 5
SSP13
R W
X
Bit 4
SSP12
R W
X
Bit 3
SSP11
R W
X
Bit 2
SSP10
R W
X
Bit 1
SSP9
R W
X
Bit 0
SSP8
R W
X
Watch Dog Hard Alarm Safe
Freq Programming bits
These bits represent the number of Watch Dog Time
Base Units that pass before the Watch Alarm expires.
Default is 7 X 290ms = 2s.
These bits configure the safe frequency that the device
returns to if the Watchdog Hardware Timer expires.
The value show here corresponds to the power up
default of the device. See the various Frequency Select
Tables for the exact frequencies.
The decimal representation of M and N Divider in Byte
16 and 17 will configure the VC O frequency. Default at
power up = Byte 3 Rom table. See M/N Caculation
Tables for VCO frequency formulas.
Note: If CLKREQA and CLKREQB are both selected to control an output, the control condition is an OR function. CLKREQA# = 0
OR CLKREQB = 0 results in the controlled output running.
Spread Spectrum
Programming b(15:8)
These bits set the CPU spread pecentage.Please
contact IDT for the appropriate values.
Spread Spectrum
Programming b(7:0)
These bits set the CPU spread pecentage.Please
contact IDT for the appropriate values.
M Divider Programming bits
The decimal representation of M and N Divider in Byte
16 and 17 will configure the VC O frequency. Default at
power up = Byte 3 Rom table. See M/N Caculation
Tables for VCO frequency formulas.
N Divider Programming
b(10:3)
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