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參數(shù)資料
| 型號(hào)： | ICS932S890CKLFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 12/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK CHIP EXPRESS 72MLF |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 類型： | 時(shí)鐘/頻率合成器 |
| PLL： | 是 |
| 主要目的： | AMD CPU |
| 輸入： | 晶體 |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:27 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 212.24MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 72-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 72-VFQFPN（10x10） |
| 包裝： | 帶卷 (TR) |
932S890C
RD890 SYSTEM CLOCK FOR AMD-BASED SERVERS
IDT
RD890 SYSTEM CLOCK FOR AMD-BASED SERVERS
2
932S890C
REV D 052011
Pin Descriptions
PIN #
PIN NAME
PIN TYPE
D ESCRIPTION
1
VDDSATA_3.3
PWR
Power supply for SATA core logic, nominal 3.3V
2
SATAC_LPRS
OUT
Complement clock of low pow er differential SATA clock pair. (no 50 ohm shunt resistor to GN D and no 33 ohm
series resistor needed)
3SATAT_LPRS
OUT
True clock of low power differential SATA clock pair. (no 50 ohm shunt resistor to GND and no 33 ohm series
resistor needed)
4
GNDSATA
GND
Ground pin for the SATA output
5
CPUKG0C_LPRS
OUT
Complementary signal of low-power differential push-pull AMD "Greyhound" clock w ith integrated series resistor.
(no 33 ohm series resistor needed and no 50 ohm pull down resistor needed)
6CPUKG0T_LPRS
OUT
True signal of low-power differential push-pull AMD "Greyhound" CPU clock with integrated series resistor(no 33
ohm series resistor needed and no 50 ohm pull down resistor needed)
7
CPUKG1C_LPRS
OUT
Complementary signal of low-power differential push-pull AMD "Greyhound" CPU clock with integrated series
resistor. (no 33 ohm series resistor needed and no 50 ohm pull down resistor needed)
8CPUKG1T_LPRS
OUT
True signal of low-power differential push-pull AMD "Greyhound" CPU clock with integrated series resistor(no 33
ohm series resistor needed and no 50 ohm pull down resistor needed)
9
VDDCPU_3.3
PWR
Supply for CPU core and outputs, 3.3V nominal
10
GNDCPU
GND
Ground pin for the CPU outputs
11
CPUKG2C_LPRS
OUT
Complementary signal of low-power differential push-pull AMD "Greyhound" CPU clock with integrated series
resistor. (no 33 ohm series resistor needed and no 50 ohm pull down resistor needed)
12
CPUKG2T_LPRS
OUT
True signal of low-power differential push-pull AMD "Greyhound" CPU clock with integrated series resistor(no 33
ohm series resistor needed and no 50 ohm pull down resistor needed)
13
CPUKG3C_LPRS
OUT
Complementary signal of low-power differential push-pull AMD "Greyhound" CPU clock with integrated series
resistor. (no 33 ohm series resistor needed and no 50 ohm pull down resistor needed)
14
CPUKG3T_LPRS
OUT
True signal of low-power differential push-pull AMD "Greyhound" CPU clock with integrated series resistor(no 33
ohm series resistor needed and no 50 ohm pull down resistor needed)
15
RESTORE#
I/O
Open Drain I/O. As an input it restores the PLL's to power up default state. As an output, this signal is driven low
when the internal watchdog hardware timer expires. It is cleared when the internal watchdog hardware timer is
reset or disabled. The input is falling edge triggered.
0 = Restore Settings, 1 = normal operation.
16
HTT0C _LPRS
OUT
Complementary signal of low-pow er differential push-pull Hypertransport 3 clock with integrated series resistor.
(no 50 ohm shunt resistor to GND and no 33 ohm series resistor needed)
17
HTT0T_LPRS
OUT
True signal of low-power differential push-pull Hypertransport 3 clock with integrated series resistor. (no 50 ohm
shunt resistor to GND and no 33 ohm series resistor needed)
18
GNDHTT
PWR
Ground pin for the HTT outputs
19
VDDHTT_3.3
PWR
Supply for HTT clocks, nominal 3.3V.
20
HTT1C _LPRS
OUT
Complementary signal of low-pow er differential push-pull Hypertransport 3 clock with integrated series resistor.
(no 50 ohm shunt resistor to GND and no 33 ohm series resistor needed)
21
HTT1T_LPRS
OUT
True signal of low-power differential push-pull Hypertransport 3 clock with integrated series resistor. (no 50 ohm
shunt resistor to GND and no 33 ohm series resistor needed)
22
SMBCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
23
SMBDAT
I/O
Data pin for SMBus circuitry, 5V tolerant.
24
X1
IN
Crystal input, nominally 14.318MHz
25
X2
OUT
Crystal output, nominally 14.318MHz
26
VDDREF_3.3
PWR
Ref, XTAL pow er supply, nominal 3.3V
27
REF0
OUT
14.318 MHz reference clock, 3.3V
28
REF1
OUT
14.318 MHz reference clock, 3.3V
29
GNDREF
GND
Ground pin for the REF outputs.
30
GND48
GND
Ground pin for the 48MHz outputs
31
48MHz_0
OUT
48MHz clock output.
32
48MHz_1
OUT
48MHz clock output. (180 degrees out of phase with 48MHz_0)
33
VDD48_3.3
PWR
Power pin for the 48MHz and SIO outputs and core. 3.3V
34
SIO_0_1.8/SIO_SEL
I/O
Selectable 48MHz or 24MHz output/SIO Select Latched Input
0 = 24MHz, 1 = 48MHz.
35
SIO_1_1.8
OUT
Selectable 48MHz or 24MHz output. (180 out of phase with SIO 0. Selected by SIO latched input.
0 = 24MHz, 1 = 48MHz.
36
GNDSIO
GND
Ground pin for the SIO outputs
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