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參數(shù)資料
| 型號： | ICS932S890CKLFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 20/21頁 |
| 文件大小： | 0K |
| 描述： | IC CLK CHIP EXPRESS 72MLF |
| 標準包裝： | 500 |
| 類型： | 時鐘/頻率合成器 |
| PLL： | 是 |
| 主要目的： | AMD CPU |
| 輸入： | 晶體 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:27 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 212.24MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 72-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 72-VFQFPN（10x10） |
| 包裝： | 帶卷 (TR) |
932S890C
RD890 SYSTEM CLOCK FOR AMD-BASED SERVERS
IDT
RD890 SYSTEM CLOCK FOR AMD-BASED SERVERS
8
932S890C
REV D 052011
AC Electrical Characteristics–Low-Power DIF Outputs: CPUKG and HTT
PARA METER
SY MBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
Crossing Point Variation
ΔV
CROSS
Single-ended Measurement
14 0
mV
1,2,5
CPU Frequency
(HTT = 1/2 of CPU Frequency)
f
CPU
Spread S pecturm On
198.8
20 0
MHz
1,3
Long Term Accuracy
p pm
Spread Specturm Off
-50
+50
ppm
1,11
Rising Edge Slew Rate
SRISE
Differential Measurement
0.5
10
V/ns
1,4
Falling Edge Slew Rate
SFALL
Differential Measurement
0.5
10
V/ns
1,4
Slew Rate Variation
tSLVAR
Single-ended Measurement
20
%
1
CPU, DIF HTT Jitter - Cycle to
Cycle
CPUJ
C2 C
Differential Measurement
15 0
ps
1,6
Accumulated Jitter
t
JACC
See Notes
1
ns
1,7
Peak to Peak Differential
Voltage
V
D(PK- PK)
Differential Measurement
400
2400
mV
1,8
Differential Voltage
VD
Differential Measurement
200
1200
mV
1,9
Duty Cycle
DCYC
Differential Measurement
45
55
%
1
Amplitude Variatio n
ΔV
D
Change in V D DC cycle to cycle
-75
75
mV
1,10
CPU[3:0] Skew
CPU
SKEW3 0
Differential Measurement
20 0
ps
1
HTT[1:0] Skew
HTT
SKEW10
Differential Measurement
10 0
ps
1
1 Guaranteed by design and characterization, not 100% tested in production.
3 Minimum Frequency is a result of 0.5% down spread spectrum
6 Max difference of t
CYC LE between a ny tw o adjacent cycles.
7 Accumulated tjc over a 10 s time period, measured with JIT2 TIE at 50ps interval.
8 VD(PK-PK) is the overall magnitude of the differential signal.
11 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
2 Single-ended measurement at crossing point. Value is maximum – minimum over all time. DC value of common mode is not
important due to the blocking cap.
10 The difference in magnitude of two adjacent VD_DC measurements. VD_DC is the stable post overshoot and ring-back part of
the signal.
5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of
CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets
CLK#.
4 Differential measurement through the range of ±100 mV, differential signal must remain monotonic and within slew rate spec
when crossing through this region.
9
V D(min) is the amplitude of the ring-back differential measurement, guaranteed by design, that ring-back will not cross 0V VD.
VD(max) i s the largest amplitude al lowed.
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